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/linux/Documentation/devicetree/bindings/pci/
H A Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
22 clock-names:
26 num-lanes:
29 fsl,imx7d-pcie-phy:
31 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
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/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mm-iot-gateway.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 #include "imx8mm-ucm-som.dtsi"
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 compatible = "compulab,imx8mm-iot-gateway", "compulab,imx8mm-ucm-som", "fsl,imx8mm";
11 regulator-usbhub-ena {
12 compatible = "regulator-fixed";
13 regulator-name = "usbhub_ena";
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
17 enable-active-high;
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H A Dimx8mm-innocomm-wb15.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 reg_modem: regulator-modem {
11 compatible = "regulator-fixed";
12 pinctrl-names = "default";
13 pinctrl-0 = <&pinctrl_modem_regulator>;
14 regulator-min-microvolt = <3300000>;
15 regulator-max-microvolt = <3300000>;
16 regulator-name = "epdev_on";
18 enable-active-high;
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H A Dimx8mm-phyboard-polis-rdk.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include "imx8mm-phycore-som.dtsi"
15 model = "PHYTEC phyBOARD-Polis-i.MX8MM RDK";
16 compatible = "phytec,imx8mm-phyboard-polis-rdk",
17 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
20 stdout-path = &uart3;
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H A Dimx8mm-beacon-baseboard.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 dmic_codec: dmic-codec {
11 compatible = "dmic-codec";
12 num-channels = <1>;
13 #sound-dai-cells = <0>;
17 compatible = "gpio-leds";
22 default-state = "off";
28 default-state = "off";
34 default-state = "off";
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H A Dimx8mm-phygate-tauri-l.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/input/linux-event-codes.h>
9 #include <dt-bindings/leds/common.h>
10 #include <dt-bindings/phy/phy-imx8-pcie.h>
11 #include "imx8mm-phycore-som.dtsi"
14 model = "PHYTEC phyGATE-Tauri-L-iMX8MM";
15 compatible = "phytec,imx8mm-phygate-tauri-l",
16 "phytec,imx8mm-phycore-som", "fsl,imx8mm";
19 stdout-path = &uart3;
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H A Dimx8mm-evk.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 #include <dt-bindings/usb/pd.h>
14 stdout-path = &uart2;
22 hdmi-connector {
23 compatible = "hdmi-connector";
29 remote-endpoint = <&adv7535_out>;
35 compatible = "gpio-leds";
36 pinctrl-names = "default";
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H A Dimx8mm-data-modul-edm-sbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/net/qca-ar803x.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
14 compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
22 stdout-path = &uart3;
32 compatible = "pwm-backlight";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_panel_backlight>;
35 brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
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H A Dimx8mm-verdin.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
7 #include <dt-bindings/pwm/pwm.h>
9 #include "imx8mm-overdrive.dtsi"
13 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 brightness-levels = <0 45 63 88 119 158 203 255>;
24 default-brightness-level = <4>;
26 enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
27 pinctrl-names = "default";
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/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on()
86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on()
87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on()
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/linux/drivers/pci/controller/dwc/
H A Dpci-imx6.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
36 #include "pcie-designware.h"
58 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
86 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
143 /* PCIe Port Logic registers (memory-mapped) */
156 /* PHY registers (not memory-mapped) */
193 WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && in imx_pcie_grp_offset()
194 imx_pcie->drvdata->variant != IMX8MQ_EP && in imx_pcie_grp_offset()
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