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/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,tegra20-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra Power Management Controller (PMC)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra20-pmc
17 - nvidia,tegra30-pmc
18 - nvidia,tegra114-pmc
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra210-p2530.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra210.dtsi"
5 model = "NVIDIA Tegra210 P2530 main board";
6 compatible = "nvidia,p2530", "nvidia,tegra210";
14 stdout-path = "serial0:115200n8";
24 /delete-property/ dmas;
25 /delete-property/ dma-names;
31 clock-frequency = <400000>;
34 pmc@7000e400 {
35 nvidia,invert-interrupt;
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H A Dtegra210.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra210-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra210-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/reset/tegra210-car.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/tegra124-soctherm.h>
10 #include <dt-bindings/soc/tegra-pmc.h>
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H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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H A Dtegra210-p2180.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/mfd/max77620.h>
4 #include "tegra210.dtsi"
8 compatible = "nvidia,p2180", "nvidia,tegra210";
18 stdout-path = "serial0:115200n8";
27 vdd-supply = <&vdd_gpu>;
33 /delete-property/ dmas;
34 /delete-property/ dma-names;
39 /delete-property/ reg-shift;
41 compatible = "nvidia,tegra30-hsuart";
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H A Dtegra234.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/clock/tegra234-clock.h>
4 #include <dt-bindings/gpio/tegra234-gpio.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/mailbox/tegra186-hsp.h>
7 #include <dt-bindings/memory/tegra234-mc.h>
8 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
9 #include <dt-bindings/power/tegra234-powergate.h>
10 #include <dt-bindings/reset/tegra234-reset.h>
11 #include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
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H A Dtegra210-p3450-0000.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/linux-event-codes.h>
6 #include <dt-bindings/mfd/max77620.h>
8 #include "tegra210.dtsi"
12 compatible = "nvidia,p3450-0000", "nvidia,tegra210";
22 stdout-path = "serial0:115200n8";
33 hvddio-pex-supply = <&vdd_1v8>;
34 dvddio-pex-supply = <&vdd_pex_1v05>;
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H A Dtegra210-p2894.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/mfd/max77620.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
7 #include "tegra210.dtsi"
16 stdout-path = "serial0:115200n8";
26 pinctrl-names = "boot";
27 pinctrl-0 = <&state_boot>;
35 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
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/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 XUSB pad controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
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/linux/drivers/gpu/drm/tegra/
H A Dvic.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
17 #include <soc/tegra/pmc.h>
52 writel(value, vic->regs + offset); in vic_writel()
61 if (vic->config->supports_sid && tegra_dev_iommu_get_stream_id(vic->dev, &stream_id)) { in vic_boot()
88 err = falcon_boot(&vic->falcon); in vic_boot()
92 hdr = vic->falcon.firmware.virt; in vic_boot()
97 hdr = vic->falcon.firmware.virt + in vic_boot()
101 falcon_execute_method(&vic->falcon, VIC_SET_FCE_UCODE_SIZE, in vic_boot()
104 &vic->falcon, VIC_SET_FCE_UCODE_OFFSET, in vic_boot()
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/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/soc/tegra/pmc.c
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
55 #include <soc/tegra/pmc.h>
57 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/linux/drivers/gpio/
H A Dgpio-tegra.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-tegra/gpio.c
6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
32 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
46 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
47 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
48 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
49 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
50 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
51 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
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/linux/drivers/pci/controller/
H A Dpci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 * Bits taken from arch/arm/mach-dove/pcie.c
26 #include <linux/irqchip/irq-msi-lib.h>
46 #include <soc/tegra/pmc.h>
258 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
380 writel(value, pcie->afi + offset); in afi_writel()
385 return readl(pcie->afi + offset); in afi_readl()
391 writel(value, pcie->pads + offset); in pads_writel()
396 return readl(pcie->pads + offset); in pads_readl()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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