Lines Matching +full:tegra210 +full:- +full:pmc
1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-tegra/gpio.c
6 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
32 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
46 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
47 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
48 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
49 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
50 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
51 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
52 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
67 * IRQ-core code uses raw locking, and thus, nested locking also
106 writel_relaxed(val, tgi->regs + reg); in tegra_gpio_writel()
111 return readl_relaxed(tgi->regs + reg); in tegra_gpio_readl()
180 dev_err(tgi->dev, in tegra_gpio_direction_input()
182 chip->base + offset, ret); in tegra_gpio_direction_input()
200 dev_err(tgi->dev, in tegra_gpio_direction_output()
202 chip->base + offset, ret); in tegra_gpio_direction_output()
216 return -EINVAL; in tegra_gpio_get_direction()
230 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)]; in tegra_gpio_set_debounce()
247 spin_lock_irqsave(&bank->dbc_lock[port], flags); in tegra_gpio_set_debounce()
248 if (bank->dbc_cnt[port] < debounce_ms) { in tegra_gpio_set_debounce()
250 bank->dbc_cnt[port] = debounce_ms; in tegra_gpio_set_debounce()
252 spin_unlock_irqrestore(&bank->dbc_lock[port], flags); in tegra_gpio_set_debounce()
265 return -ENOTSUPP; in tegra_gpio_set_config()
275 unsigned int gpio = d->hwirq; in tegra_gpio_irq_ack()
284 unsigned int gpio = d->hwirq; in tegra_gpio_irq_mask()
294 unsigned int gpio = d->hwirq; in tegra_gpio_irq_unmask()
302 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type; in tegra_gpio_irq_set_type()
310 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; in tegra_gpio_irq_set_type()
334 return -EINVAL; in tegra_gpio_irq_set_type()
337 raw_spin_lock_irqsave(&bank->lvl_lock[port], flags); in tegra_gpio_irq_set_type()
344 raw_spin_unlock_irqrestore(&bank->lvl_lock[port], flags); in tegra_gpio_irq_set_type()
349 ret = gpiochip_lock_as_irq(&tgi->gc, gpio); in tegra_gpio_irq_set_type()
351 dev_err(tgi->dev, in tegra_gpio_irq_set_type()
362 if (d->parent_data) in tegra_gpio_irq_set_type()
372 unsigned int gpio = d->hwirq; in tegra_gpio_irq_shutdown()
375 gpiochip_unlock_as_irq(&tgi->gc, gpio); in tegra_gpio_irq_shutdown()
382 struct irq_domain *domain = tgi->gc.irq.domain; in tegra_gpio_irq_handler()
390 for (i = 0; i < tgi->bank_count; i++) { in tegra_gpio_irq_handler()
391 if (tgi->irqs[i] == irq) { in tegra_gpio_irq_handler()
392 bank = &tgi->bank_info[i]; in tegra_gpio_irq_handler()
403 gpio = tegra_gpio_compose(bank->bank, port, 0); in tegra_gpio_irq_handler()
438 *parent_hwirq = chip->irq.child_offset_to_irq(chip, hwirq); in tegra_gpio_child_to_parent_hwirq()
449 struct irq_fwspec *fwspec = &gfwspec->fwspec; in tegra_gpio_populate_parent_fwspec()
451 fwspec->fwnode = chip->irq.parent_domain->fwnode; in tegra_gpio_populate_parent_fwspec()
452 fwspec->param_count = 3; in tegra_gpio_populate_parent_fwspec()
453 fwspec->param[0] = 0; in tegra_gpio_populate_parent_fwspec()
454 fwspec->param[1] = parent_hwirq; in tegra_gpio_populate_parent_fwspec()
455 fwspec->param[2] = parent_type; in tegra_gpio_populate_parent_fwspec()
466 for (b = 0; b < tgi->bank_count; b++) { in tegra_gpio_resume()
467 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; in tegra_gpio_resume()
469 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { in tegra_gpio_resume()
472 tegra_gpio_writel(tgi, bank->cnf[p], in tegra_gpio_resume()
475 if (tgi->soc->debounce_supported) { in tegra_gpio_resume()
476 tegra_gpio_writel(tgi, bank->dbc_cnt[p], in tegra_gpio_resume()
478 tegra_gpio_writel(tgi, bank->dbc_enb[p], in tegra_gpio_resume()
482 tegra_gpio_writel(tgi, bank->out[p], in tegra_gpio_resume()
484 tegra_gpio_writel(tgi, bank->oe[p], in tegra_gpio_resume()
486 tegra_gpio_writel(tgi, bank->int_lvl[p], in tegra_gpio_resume()
488 tegra_gpio_writel(tgi, bank->int_enb[p], in tegra_gpio_resume()
501 for (b = 0; b < tgi->bank_count; b++) { in tegra_gpio_suspend()
502 struct tegra_gpio_bank *bank = &tgi->bank_info[b]; in tegra_gpio_suspend()
504 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { in tegra_gpio_suspend()
507 bank->cnf[p] = tegra_gpio_readl(tgi, in tegra_gpio_suspend()
509 bank->out[p] = tegra_gpio_readl(tgi, in tegra_gpio_suspend()
511 bank->oe[p] = tegra_gpio_readl(tgi, in tegra_gpio_suspend()
513 if (tgi->soc->debounce_supported) { in tegra_gpio_suspend()
514 bank->dbc_enb[p] = tegra_gpio_readl(tgi, in tegra_gpio_suspend()
516 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) | in tegra_gpio_suspend()
517 bank->dbc_enb[p]; in tegra_gpio_suspend()
520 bank->int_enb[p] = tegra_gpio_readl(tgi, in tegra_gpio_suspend()
522 bank->int_lvl[p] = tegra_gpio_readl(tgi, in tegra_gpio_suspend()
526 tegra_gpio_writel(tgi, bank->wake_enb[p], in tegra_gpio_suspend()
539 unsigned int gpio = d->hwirq; in tegra_gpio_irq_set_wake()
543 bank = &tgi->bank_info[GPIO_BANK(d->hwirq)]; in tegra_gpio_irq_set_wake()
549 err = irq_set_irq_wake(tgi->irqs[bank->bank], enable); in tegra_gpio_irq_set_wake()
553 if (d->parent_data) { in tegra_gpio_irq_set_wake()
556 irq_set_irq_wake(tgi->irqs[bank->bank], !enable); in tegra_gpio_irq_set_wake()
562 bank->wake_enb[port] |= mask; in tegra_gpio_irq_set_wake()
564 bank->wake_enb[port] &= ~mask; in tegra_gpio_irq_set_wake()
574 if (data->parent_data) in tegra_gpio_irq_set_affinity()
577 return -EINVAL; in tegra_gpio_irq_set_affinity()
585 tegra_gpio_enable(tgi, d->hwirq); in tegra_gpio_irq_request_resources()
587 return gpiochip_reqres_irq(chip, d->hwirq); in tegra_gpio_irq_request_resources()
595 gpiochip_relres_irq(chip, d->hwirq); in tegra_gpio_irq_release_resources()
596 tegra_gpio_enable(tgi, d->hwirq); in tegra_gpio_irq_release_resources()
603 seq_printf(s, dev_name(chip->parent)); in tegra_gpio_irq_print_chip()
643 struct tegra_gpio_info *tgi = dev_get_drvdata(s->private); in tegra_dbg_gpio_show()
646 for (i = 0; i < tgi->bank_count; i++) { in tegra_dbg_gpio_show()
667 debugfs_create_devm_seqfile(tgi->dev, "tegra_gpio", NULL, in tegra_gpio_debuginit()
684 { .compatible = "nvidia,tegra210-pmc", },
697 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL); in tegra_gpio_probe()
699 return -ENODEV; in tegra_gpio_probe()
701 tgi->soc = of_device_get_match_data(&pdev->dev); in tegra_gpio_probe()
702 tgi->dev = &pdev->dev; in tegra_gpio_probe()
708 tgi->bank_count = ret; in tegra_gpio_probe()
710 if (!tgi->bank_count) { in tegra_gpio_probe()
711 dev_err(&pdev->dev, "Missing IRQ resource\n"); in tegra_gpio_probe()
712 return -ENODEV; in tegra_gpio_probe()
715 tgi->gc.label = "tegra-gpio"; in tegra_gpio_probe()
716 tgi->gc.request = pinctrl_gpio_request; in tegra_gpio_probe()
717 tgi->gc.free = tegra_gpio_free; in tegra_gpio_probe()
718 tgi->gc.direction_input = tegra_gpio_direction_input; in tegra_gpio_probe()
719 tgi->gc.get = tegra_gpio_get; in tegra_gpio_probe()
720 tgi->gc.direction_output = tegra_gpio_direction_output; in tegra_gpio_probe()
721 tgi->gc.set = tegra_gpio_set; in tegra_gpio_probe()
722 tgi->gc.get_direction = tegra_gpio_get_direction; in tegra_gpio_probe()
723 tgi->gc.base = 0; in tegra_gpio_probe()
724 tgi->gc.ngpio = tgi->bank_count * 32; in tegra_gpio_probe()
725 tgi->gc.parent = &pdev->dev; in tegra_gpio_probe()
729 if (tgi->soc->debounce_supported) in tegra_gpio_probe()
730 tgi->gc.set_config = tegra_gpio_set_config; in tegra_gpio_probe()
732 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count, in tegra_gpio_probe()
733 sizeof(*tgi->bank_info), GFP_KERNEL); in tegra_gpio_probe()
734 if (!tgi->bank_info) in tegra_gpio_probe()
735 return -ENOMEM; in tegra_gpio_probe()
737 tgi->irqs = devm_kcalloc(&pdev->dev, tgi->bank_count, in tegra_gpio_probe()
738 sizeof(*tgi->irqs), GFP_KERNEL); in tegra_gpio_probe()
739 if (!tgi->irqs) in tegra_gpio_probe()
740 return -ENOMEM; in tegra_gpio_probe()
742 for (i = 0; i < tgi->bank_count; i++) { in tegra_gpio_probe()
747 bank = &tgi->bank_info[i]; in tegra_gpio_probe()
748 bank->bank = i; in tegra_gpio_probe()
750 tgi->irqs[i] = ret; in tegra_gpio_probe()
753 raw_spin_lock_init(&bank->lvl_lock[j]); in tegra_gpio_probe()
754 spin_lock_init(&bank->dbc_lock[j]); in tegra_gpio_probe()
758 irq = &tgi->gc.irq; in tegra_gpio_probe()
759 irq->fwnode = dev_fwnode(&pdev->dev); in tegra_gpio_probe()
760 irq->child_to_parent_hwirq = tegra_gpio_child_to_parent_hwirq; in tegra_gpio_probe()
761 irq->populate_parent_alloc_arg = tegra_gpio_populate_parent_fwspec; in tegra_gpio_probe()
762 irq->handler = handle_simple_irq; in tegra_gpio_probe()
763 irq->default_type = IRQ_TYPE_NONE; in tegra_gpio_probe()
764 irq->parent_handler = tegra_gpio_irq_handler; in tegra_gpio_probe()
765 irq->parent_handler_data = tgi; in tegra_gpio_probe()
766 irq->num_parents = tgi->bank_count; in tegra_gpio_probe()
767 irq->parents = tgi->irqs; in tegra_gpio_probe()
771 irq->parent_domain = irq_find_host(np); in tegra_gpio_probe()
774 if (!irq->parent_domain) in tegra_gpio_probe()
775 return -EPROBE_DEFER; in tegra_gpio_probe()
782 tgi->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_gpio_probe()
783 if (IS_ERR(tgi->regs)) in tegra_gpio_probe()
784 return PTR_ERR(tgi->regs); in tegra_gpio_probe()
786 for (i = 0; i < tgi->bank_count; i++) { in tegra_gpio_probe()
794 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi); in tegra_gpio_probe()
820 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
821 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
822 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
829 .name = "tegra-gpio",