Lines Matching +full:tegra210 +full:- +full:pmc
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
17 #include <soc/tegra/pmc.h>
488 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
490 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
498 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
499 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
506 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
508 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
512 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
535 * Implementing ->set_parent() here isn't really required because the parent
545 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent()
569 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent()
603 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
605 return ERR_PTR(-ENOMEM); in tegra_clk_sor_pad_register()
607 pad->sor = sor; in tegra_clk_sor_pad_register()
611 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; in tegra_clk_sor_pad_register()
612 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); in tegra_clk_sor_pad_register()
615 pad->hw.init = &init; in tegra_clk_sor_pad_register()
617 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
624 struct drm_dp_link *link = &sor->link; in tegra_sor_filter_rates()
628 for (i = 0; i < link->num_rates; i++) { in tegra_sor_filter_rates()
629 switch (link->rates[i]) { in tegra_sor_filter_rates()
637 link->rates[i]); in tegra_sor_filter_rates()
638 link->rates[i] = 0; in tegra_sor_filter_rates()
655 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
658 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
659 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
661 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
662 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
665 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
667 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
670 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
672 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
674 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
692 return -ETIMEDOUT; in tegra_sor_power_up_lanes()
703 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
706 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
724 return -ETIMEDOUT; in tegra_sor_power_down_lanes()
733 /* pre-charge all used lanes */ in tegra_sor_dp_precharge()
734 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
737 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
738 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); in tegra_sor_dp_precharge()
740 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
741 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); in tegra_sor_dp_precharge()
744 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
746 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
749 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
751 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
753 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
757 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
760 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
768 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
770 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
772 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
774 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
779 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
782 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
786 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
796 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
799 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
801 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
808 const struct tegra_sor_soc *soc = sor->soc; in tegra_sor_dp_link_apply_training()
812 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
813 u8 vs = link->train.request.voltage_swing[i]; in tegra_sor_dp_link_apply_training()
814 u8 pe = link->train.request.pre_emphasis[i]; in tegra_sor_dp_link_apply_training()
815 u8 pc = link->train.request.post_cursor[i]; in tegra_sor_dp_link_apply_training()
816 u8 shift = sor->soc->lane_map[i] << 3; in tegra_sor_dp_link_apply_training()
818 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
819 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
820 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
822 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) in tegra_sor_dp_link_apply_training()
823 tx_pu = sor->soc->tx_pu[pc][vs][pe]; in tegra_sor_dp_link_apply_training()
825 switch (link->train.pattern) { in tegra_sor_dp_link_apply_training()
847 return -EINVAL; in tegra_sor_dp_link_apply_training()
850 if (link->caps.channel_coding) in tegra_sor_dp_link_apply_training()
859 if (link->caps.tps3_supported) in tegra_sor_dp_link_apply_training()
864 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
868 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
882 rate = drm_dp_link_rate_to_bw_code(link->rate); in tegra_sor_dp_link_configure()
883 lanes = link->lanes; in tegra_sor_dp_link_configure()
895 if (link->caps.enhanced_framing) in tegra_sor_dp_link_configure()
903 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
920 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
925 if (link->edp == 0) in tegra_sor_dp_link_configure()
934 dev_err(sor->dev, "failed to power down lanes: %d\n", err); in tegra_sor_dp_link_configure()
938 /* power up and pre-charge lanes */ in tegra_sor_dp_link_configure()
941 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", in tegra_sor_dp_link_configure()
996 return -ETIMEDOUT; in tegra_sor_setup_pwm()
1026 return -ETIMEDOUT; in tegra_sor_attach()
1046 return -ETIMEDOUT; in tegra_sor_wakeup()
1067 return -ETIMEDOUT; in tegra_sor_power_up()
1091 const u64 f = params->precision; in tegra_sor_compute_params()
1094 active_sym = params->ratio * tu_size; in tegra_sor_compute_params()
1096 frac = active_sym - active_count; in tegra_sor_compute_params()
1101 frac = f - frac; in tegra_sor_compute_params()
1124 approx = active_count + (active_frac * (f - 1)) * f; in tegra_sor_compute_params()
1136 error = div_s64(active_sym - approx, tu_size); in tegra_sor_compute_params()
1137 error *= params->num_clocks; in tegra_sor_compute_params()
1139 if (error <= 0 && abs(error) < params->error) { in tegra_sor_compute_params()
1140 params->active_count = div_u64(active_count, f); in tegra_sor_compute_params()
1141 params->active_polarity = active_polarity; in tegra_sor_compute_params()
1142 params->active_frac = active_frac; in tegra_sor_compute_params()
1143 params->error = abs(error); in tegra_sor_compute_params()
1144 params->tu_size = tu_size; in tegra_sor_compute_params()
1158 const u64 f = 100000, link_rate = link->rate * 1000; in tegra_sor_compute_config()
1159 const u64 pclk = (u64)mode->clock * 1000; in tegra_sor_compute_config()
1165 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) in tegra_sor_compute_config()
1166 return -EINVAL; in tegra_sor_compute_config()
1168 input = pclk * config->bits_per_pixel; in tegra_sor_compute_config()
1169 output = link_rate * 8 * link->lanes; in tegra_sor_compute_config()
1172 return -ERANGE; in tegra_sor_compute_config()
1176 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); in tegra_sor_compute_config()
1181 for (i = params.tu_size; i >= 32; i--) in tegra_sor_compute_config()
1186 config->active_polarity = 0; in tegra_sor_compute_config()
1187 config->active_count = params.active_count; in tegra_sor_compute_config()
1190 config->active_count--; in tegra_sor_compute_config()
1192 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1193 config->active_frac = 1; in tegra_sor_compute_config()
1195 config->active_polarity = params.active_polarity; in tegra_sor_compute_config()
1196 config->active_count = params.active_count; in tegra_sor_compute_config()
1197 config->active_frac = params.active_frac; in tegra_sor_compute_config()
1198 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1201 dev_dbg(sor->dev, in tegra_sor_compute_config()
1203 config->active_polarity, config->active_count, in tegra_sor_compute_config()
1204 config->tu_size, config->active_frac); in tegra_sor_compute_config()
1206 watermark = params.ratio * config->tu_size * (f - params.ratio); in tegra_sor_compute_config()
1210 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; in tegra_sor_compute_config()
1211 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * in tegra_sor_compute_config()
1212 (link->lanes * 8); in tegra_sor_compute_config()
1214 if (config->watermark > 30) { in tegra_sor_compute_config()
1215 config->watermark = 30; in tegra_sor_compute_config()
1216 dev_err(sor->dev, in tegra_sor_compute_config()
1218 config->watermark); in tegra_sor_compute_config()
1219 } else if (config->watermark > num_syms_per_line) { in tegra_sor_compute_config()
1220 config->watermark = num_syms_per_line; in tegra_sor_compute_config()
1221 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
1222 config->watermark); in tegra_sor_compute_config()
1226 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; in tegra_sor_compute_config()
1227 config->hblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1229 if (link->caps.enhanced_framing) in tegra_sor_compute_config()
1230 config->hblank_symbols -= 3; in tegra_sor_compute_config()
1232 config->hblank_symbols -= 12 / link->lanes; in tegra_sor_compute_config()
1235 num = (mode->hdisplay - 25) * link_rate; in tegra_sor_compute_config()
1236 config->vblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1237 config->vblank_symbols -= 36 / link->lanes + 4; in tegra_sor_compute_config()
1239 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
1240 config->vblank_symbols); in tegra_sor_compute_config()
1252 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1257 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1260 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1263 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1265 if (config->active_polarity) in tegra_sor_apply_config()
1276 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1281 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1289 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1299 SOR_STATE_ASY_OWNER(dc->pipe + 1); in tegra_sor_mode_set()
1301 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in tegra_sor_mode_set()
1304 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tegra_sor_mode_set()
1307 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in tegra_sor_mode_set()
1310 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tegra_sor_mode_set()
1313 switch (state->bpc) { in tegra_sor_mode_set()
1346 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1347 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1349 /* sync end = sync width - 1 */ in tegra_sor_mode_set()
1350 vse = mode->vsync_end - mode->vsync_start - 1; in tegra_sor_mode_set()
1351 hse = mode->hsync_end - mode->hsync_start - 1; in tegra_sor_mode_set()
1354 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1357 vbe = vse + (mode->vtotal - mode->vsync_end); in tegra_sor_mode_set()
1358 hbe = hse + (mode->htotal - mode->hsync_end); in tegra_sor_mode_set()
1361 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1364 vbs = vbe + mode->vdisplay; in tegra_sor_mode_set()
1365 hbs = hbe + mode->hdisplay; in tegra_sor_mode_set()
1368 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1371 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1393 return -ETIMEDOUT; in tegra_sor_detach()
1418 return -ETIMEDOUT; in tegra_sor_detach()
1444 return -ETIMEDOUT; in tegra_sor_power_down()
1447 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1449 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1453 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1455 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1459 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1461 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1463 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1466 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1487 return -ETIMEDOUT; in tegra_sor_crc_wait()
1492 struct drm_info_node *node = s->private; in tegra_sor_show_crc()
1493 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc()
1494 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1495 struct drm_device *drm = node->minor->dev; in tegra_sor_show_crc()
1501 if (!crtc || !crtc->state->active) { in tegra_sor_show_crc()
1502 err = -EBUSY; in tegra_sor_show_crc()
1654 struct drm_info_node *node = s->private; in tegra_sor_show_regs()
1655 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs()
1656 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1657 struct drm_device *drm = node->minor->dev; in tegra_sor_show_regs()
1663 if (!crtc || !crtc->state->active) { in tegra_sor_show_regs()
1664 err = -EBUSY; in tegra_sor_show_regs()
1671 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, in tegra_sor_show_regs()
1689 struct drm_minor *minor = connector->dev->primary; in tegra_sor_late_register()
1690 struct dentry *root = connector->debugfs_entry; in tegra_sor_late_register()
1693 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1695 if (!sor->debugfs_files) in tegra_sor_late_register()
1696 return -ENOMEM; in tegra_sor_late_register()
1699 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1701 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1712 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1713 connector->debugfs_entry, in tegra_sor_early_unregister()
1714 connector->dev->primary); in tegra_sor_early_unregister()
1715 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1716 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1727 if (connector->state) { in tegra_sor_connector_reset()
1728 __drm_atomic_helper_connector_destroy_state(connector->state); in tegra_sor_connector_reset()
1729 kfree(connector->state); in tegra_sor_connector_reset()
1732 __drm_atomic_helper_connector_reset(connector, &state->base); in tegra_sor_connector_reset()
1741 if (sor->aux) in tegra_sor_connector_detect()
1742 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1750 struct tegra_sor_state *state = to_sor_state(connector->state); in tegra_sor_connector_duplicate_state()
1757 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); in tegra_sor_connector_duplicate_state()
1759 return ©->base; in tegra_sor_connector_duplicate_state()
1779 if (sor->aux) in tegra_sor_connector_get_modes()
1780 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1784 if (sor->aux) in tegra_sor_connector_get_modes()
1785 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1809 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_sor_encoder_atomic_check()
1810 unsigned long pclk = crtc_state->mode.clock * 1000; in tegra_sor_encoder_atomic_check()
1815 info = &output->connector.display_info; in tegra_sor_encoder_atomic_check()
1822 state->link_speed = 20; in tegra_sor_encoder_atomic_check()
1823 state->pclk = pclk / 2; in tegra_sor_encoder_atomic_check()
1825 state->link_speed = 10; in tegra_sor_encoder_atomic_check()
1826 state->pclk = pclk; in tegra_sor_encoder_atomic_check()
1829 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1832 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); in tegra_sor_encoder_atomic_check()
1836 switch (info->bpc) { in tegra_sor_encoder_atomic_check()
1839 state->bpc = info->bpc; in tegra_sor_encoder_atomic_check()
1843 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); in tegra_sor_encoder_atomic_check()
1844 state->bpc = 8; in tegra_sor_encoder_atomic_check()
1856 for (i = size; i > 0; i--) in tegra_sor_hdmi_subpack()
1857 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1884 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1897 * - subpack_low: bytes 0 - 3 in tegra_sor_hdmi_write_infopack()
1898 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) in tegra_sor_hdmi_write_infopack()
1901 size_t rem = size - i, num = min_t(size_t, rem, 4); in tegra_sor_hdmi_write_infopack()
1906 num = min_t(size_t, rem - num, 3); in tegra_sor_hdmi_write_infopack()
1930 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
1932 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1938 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1955 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
1958 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
2008 if (sor->format.channels != 2) in tegra_sor_audio_enable()
2030 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2034 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2038 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2077 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2090 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2094 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2098 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2128 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2129 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2130 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2147 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2148 drm_scdc_set_scrambling(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2155 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2156 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2173 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2174 drm_scdc_set_scrambling(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2183 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) { in tegra_sor_hdmi_scdc_work()
2188 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2193 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2196 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2198 if (mode->clock >= 340000 && scdc->supported) { in tegra_sor_hdmi_scdc_start()
2199 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2201 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2208 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_disable()
2218 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2226 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2229 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2237 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2239 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2241 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2243 host1x_client_suspend(&sor->client); in tegra_sor_hdmi_disable()
2250 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_enable()
2260 state = to_sor_state(output->connector.state); in tegra_sor_hdmi_enable()
2261 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_hdmi_enable()
2262 pclk = mode->clock * 1000; in tegra_sor_hdmi_enable()
2264 err = host1x_client_resume(&sor->client); in tegra_sor_hdmi_enable()
2266 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_hdmi_enable()
2271 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2273 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2277 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2279 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2281 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2285 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2287 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2291 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2293 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2295 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2298 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2300 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2302 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2309 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2313 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2316 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2342 if (mode->clock < 340000) { in tegra_sor_hdmi_enable()
2377 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2385 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2398 err = clk_set_parent(sor->clk_pad, sor->clk_dp); in tegra_sor_hdmi_enable()
2400 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_hdmi_enable()
2407 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2409 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_hdmi_enable()
2415 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2417 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_hdmi_enable()
2423 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2425 if (mode->clock >= 340000) in tegra_sor_hdmi_enable()
2430 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2432 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2433 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2436 if (mode->clock < 75000) in tegra_sor_hdmi_enable()
2442 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; in tegra_sor_hdmi_enable()
2448 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2451 (mode->hsync_end - mode->hsync_start) + in tegra_sor_hdmi_enable()
2452 (mode->htotal - mode->hsync_end) - 10; in tegra_sor_hdmi_enable()
2469 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2481 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2483 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2486 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2488 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2489 mode->clock * 1000); in tegra_sor_hdmi_enable()
2493 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2497 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2498 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2499 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2500 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2503 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2506 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2507 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2509 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2511 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2516 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2517 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2518 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2519 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2522 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2523 settings->drive_current[2] << 16 | in tegra_sor_hdmi_enable()
2524 settings->drive_current[1] << 8 | in tegra_sor_hdmi_enable()
2525 settings->drive_current[0] << 0; in tegra_sor_hdmi_enable()
2528 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2529 settings->preemphasis[2] << 16 | in tegra_sor_hdmi_enable()
2530 settings->preemphasis[1] << 8 | in tegra_sor_hdmi_enable()
2531 settings->preemphasis[0] << 0; in tegra_sor_hdmi_enable()
2534 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2537 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2538 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2540 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2542 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2543 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2546 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2548 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2550 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2560 switch (state->bpc) { in tegra_sor_hdmi_enable()
2578 WARN(1, "%u bits-per-color not supported\n", state->bpc); in tegra_sor_hdmi_enable()
2588 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2593 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2596 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2599 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2602 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2605 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2618 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2623 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2626 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2630 if (dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2631 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2634 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2641 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2656 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_disable()
2661 if (output->panel) in tegra_sor_dp_disable()
2662 drm_panel_disable(output->panel); in tegra_sor_dp_disable()
2668 if (output->connector.status != connector_status_disconnected) { in tegra_sor_dp_disable()
2669 err = drm_dp_link_power_down(sor->aux, &sor->link); in tegra_sor_dp_disable()
2671 dev_err(sor->dev, "failed to power down link: %d\n", in tegra_sor_dp_disable()
2677 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_dp_disable()
2683 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2695 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_disable()
2697 dev_err(sor->dev, "failed to set safe clock: %d\n", err); in tegra_sor_dp_disable()
2701 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_dp_disable()
2703 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_dp_disable()
2705 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_dp_disable()
2707 err = drm_dp_aux_disable(sor->aux); in tegra_sor_dp_disable()
2709 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); in tegra_sor_dp_disable()
2711 if (output->panel) in tegra_sor_dp_disable()
2712 drm_panel_unprepare(output->panel); in tegra_sor_dp_disable()
2714 host1x_client_suspend(&sor->client); in tegra_sor_dp_disable()
2720 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_enable()
2730 state = to_sor_state(output->connector.state); in tegra_sor_dp_enable()
2731 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_dp_enable()
2732 info = &output->connector.display_info; in tegra_sor_dp_enable()
2734 err = host1x_client_resume(&sor->client); in tegra_sor_dp_enable()
2736 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_dp_enable()
2741 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_enable()
2743 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_dp_enable()
2745 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_dp_enable()
2747 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); in tegra_sor_dp_enable()
2751 err = drm_dp_aux_enable(sor->aux); in tegra_sor_dp_enable()
2753 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); in tegra_sor_dp_enable()
2755 err = drm_dp_link_probe(sor->aux, &sor->link); in tegra_sor_dp_enable()
2757 dev_err(sor->dev, "failed to probe DP link: %d\n", err); in tegra_sor_dp_enable()
2761 err = drm_dp_link_choose(&sor->link, mode, info); in tegra_sor_dp_enable()
2763 dev_err(sor->dev, "failed to choose link: %d\n", err); in tegra_sor_dp_enable()
2765 if (output->panel) in tegra_sor_dp_enable()
2766 drm_panel_prepare(output->panel); in tegra_sor_dp_enable()
2768 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2770 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2774 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2776 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2778 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2780 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2782 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2789 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2792 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2797 if (output->panel) in tegra_sor_dp_enable()
2808 if (output->panel) in tegra_sor_dp_enable()
2819 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2825 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2829 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2842 err = clk_set_parent(sor->clk_pad, sor->clk_parent); in tegra_sor_dp_enable()
2844 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_dp_enable()
2851 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_dp_enable()
2853 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_dp_enable()
2859 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_dp_enable()
2861 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_dp_enable()
2866 /* use DP-A protocol */ in tegra_sor_dp_enable()
2879 err = drm_dp_link_train(&sor->link); in tegra_sor_dp_enable()
2881 dev_err(sor->dev, "link training failed: %d\n", err); in tegra_sor_dp_enable()
2883 dev_dbg(sor->dev, "link training succeeded\n"); in tegra_sor_dp_enable()
2885 err = drm_dp_link_power_up(sor->aux, &sor->link); in tegra_sor_dp_enable()
2887 dev_err(sor->dev, "failed to power up DP link: %d\n", err); in tegra_sor_dp_enable()
2891 config.bits_per_pixel = state->bpc * 3; in tegra_sor_dp_enable()
2893 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); in tegra_sor_dp_enable()
2895 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_dp_enable()
2900 if (output->panel) { in tegra_sor_dp_enable()
2909 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_dp_enable()
2916 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_dp_enable()
2921 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_dp_enable()
2924 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2931 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_dp_enable()
2933 if (output->panel) in tegra_sor_dp_enable()
2934 drm_panel_enable(output->panel); in tegra_sor_dp_enable()
2958 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); in tegra_sor_enable_regulator()
2965 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_hdmi_probe()
2966 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_hdmi_probe()
2967 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply), in tegra_sor_hdmi_probe()
2970 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2972 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2977 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_hdmi_probe()
2978 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_hdmi_probe()
2979 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply), in tegra_sor_hdmi_probe()
2982 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2984 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2989 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2990 if (IS_ERR(sor->hdmi_supply)) in tegra_sor_hdmi_probe()
2991 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply), in tegra_sor_hdmi_probe()
2994 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); in tegra_sor_hdmi_probe()
2996 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
3000 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3016 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_dp_probe()
3017 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_dp_probe()
3018 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_dp_probe()
3020 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_dp_probe()
3024 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_dp_probe()
3025 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_dp_probe()
3026 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_dp_probe()
3028 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_dp_probe()
3042 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_sor_init()
3049 if (!sor->aux) { in tegra_sor_init()
3050 if (sor->ops == &tegra_sor_hdmi_ops) { in tegra_sor_init()
3054 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
3059 if (sor->output.panel) { in tegra_sor_init()
3069 sor->link.ops = &tegra_sor_dp_link_ops; in tegra_sor_init()
3070 sor->link.aux = sor->aux; in tegra_sor_init()
3073 sor->output.dev = sor->dev; in tegra_sor_init()
3075 drm_connector_init_with_ddc(drm, &sor->output.connector, in tegra_sor_init()
3078 sor->output.ddc); in tegra_sor_init()
3079 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
3081 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
3083 drm_simple_encoder_init(drm, &sor->output.encoder, encoder); in tegra_sor_init()
3084 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
3086 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
3087 &sor->output.encoder); in tegra_sor_init()
3088 drm_connector_register(&sor->output.connector); in tegra_sor_init()
3090 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
3092 dev_err(client->dev, "failed to initialize output: %d\n", err); in tegra_sor_init()
3096 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
3098 if (sor->aux) { in tegra_sor_init()
3099 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
3101 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
3107 * XXX: Remove this reset once proper hand-over from firmware to in tegra_sor_init()
3110 if (sor->rst) { in tegra_sor_init()
3111 err = pm_runtime_resume_and_get(sor->dev); in tegra_sor_init()
3113 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); in tegra_sor_init()
3117 err = reset_control_acquire(sor->rst); in tegra_sor_init()
3119 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
3124 err = reset_control_assert(sor->rst); in tegra_sor_init()
3126 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
3132 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
3134 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
3140 if (sor->rst) { in tegra_sor_init()
3141 err = reset_control_deassert(sor->rst); in tegra_sor_init()
3143 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
3145 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3149 reset_control_release(sor->rst); in tegra_sor_init()
3150 pm_runtime_put(sor->dev); in tegra_sor_init()
3153 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
3155 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3159 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
3161 clk_disable_unprepare(sor->clk_safe); in tegra_sor_init()
3162 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3169 if (sor->rst) in tegra_sor_init()
3170 pm_runtime_put(sor->dev); in tegra_sor_init()
3180 tegra_output_exit(&sor->output); in tegra_sor_exit()
3182 if (sor->aux) { in tegra_sor_exit()
3183 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
3185 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
3190 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
3191 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
3192 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
3200 struct device *dev = client->dev; in tegra_sor_runtime_suspend()
3203 if (sor->rst) { in tegra_sor_runtime_suspend()
3204 err = reset_control_assert(sor->rst); in tegra_sor_runtime_suspend()
3210 reset_control_release(sor->rst); in tegra_sor_runtime_suspend()
3215 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_suspend()
3224 struct device *dev = client->dev; in tegra_sor_runtime_resume()
3233 err = clk_prepare_enable(sor->clk); in tegra_sor_runtime_resume()
3241 if (sor->rst) { in tegra_sor_runtime_resume()
3242 err = reset_control_acquire(sor->rst); in tegra_sor_runtime_resume()
3248 err = reset_control_deassert(sor->rst); in tegra_sor_runtime_resume()
3258 reset_control_release(sor->rst); in tegra_sor_runtime_resume()
3260 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_resume()
3630 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3631 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3632 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3633 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3634 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3635 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3642 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3648 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3653 sor->index = value; in tegra_sor_parse_dt()
3656 * override the default that we already set for Tegra210 and in tegra_sor_parse_dt()
3659 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3661 if (!sor->soc->supports_audio) in tegra_sor_parse_dt()
3662 sor->index = 0; in tegra_sor_parse_dt()
3664 sor->index = 1; in tegra_sor_parse_dt()
3667 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); in tegra_sor_parse_dt()
3669 /* fall back to default per-SoC XBAR configuration */ in tegra_sor_parse_dt()
3671 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3675 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3697 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3699 if (sor->ops->audio_enable) in tegra_sor_irq()
3700 sor->ops->audio_enable(sor); in tegra_sor_irq()
3702 if (sor->ops->audio_disable) in tegra_sor_irq()
3703 sor->ops->audio_disable(sor); in tegra_sor_irq()
3716 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3718 return -ENOMEM; in tegra_sor_probe()
3720 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3721 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3723 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3724 sor->soc->num_settings * in tegra_sor_probe()
3725 sizeof(*sor->settings), in tegra_sor_probe()
3727 if (!sor->settings) in tegra_sor_probe()
3728 return -ENOMEM; in tegra_sor_probe()
3730 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3732 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); in tegra_sor_probe()
3734 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3737 if (!sor->aux) in tegra_sor_probe()
3738 return -EPROBE_DEFER; in tegra_sor_probe()
3740 if (get_device(sor->aux->dev)) in tegra_sor_probe()
3741 sor->output.ddc = &sor->aux->ddc; in tegra_sor_probe()
3744 if (!sor->aux) { in tegra_sor_probe()
3745 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3746 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3747 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3748 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3749 dev_err(&pdev->dev, "LVDS not supported yet\n"); in tegra_sor_probe()
3750 return -ENODEV; in tegra_sor_probe()
3752 dev_err(&pdev->dev, "unknown (non-DP) support\n"); in tegra_sor_probe()
3753 return -ENODEV; in tegra_sor_probe()
3756 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); in tegra_sor_probe()
3763 sor->ops = &tegra_sor_dp_ops; in tegra_sor_probe()
3764 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3771 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3773 dev_err_probe(&pdev->dev, err, "failed to probe output\n"); in tegra_sor_probe()
3777 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3778 err = sor->ops->probe(sor); in tegra_sor_probe()
3780 dev_err(&pdev->dev, "failed to probe %s: %d\n", in tegra_sor_probe()
3781 sor->ops->name, err); in tegra_sor_probe()
3786 sor->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_sor_probe()
3787 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3788 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3796 sor->irq = err; in tegra_sor_probe()
3798 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3799 dev_name(sor->dev), sor); in tegra_sor_probe()
3801 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); in tegra_sor_probe()
3805 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3806 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3807 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3809 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { in tegra_sor_probe()
3810 dev_err(&pdev->dev, "failed to get reset control: %d\n", in tegra_sor_probe()
3821 sor->rst = NULL; in tegra_sor_probe()
3824 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3825 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3826 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3827 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); in tegra_sor_probe()
3831 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3832 struct device_node *np = pdev->dev.of_node; in tegra_sor_probe()
3836 * For backwards compatibility with Tegra210 device trees, in tegra_sor_probe()
3840 if (of_property_match_string(np, "clock-names", "out") < 0) in tegra_sor_probe()
3845 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3846 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3847 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3848 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3854 sor->clk_out = sor->clk; in tegra_sor_probe()
3857 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3858 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3859 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3860 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); in tegra_sor_probe()
3864 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3865 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3866 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3867 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); in tegra_sor_probe()
3871 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3872 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3873 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3874 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); in tegra_sor_probe()
3882 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3883 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3884 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3885 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3891 * we're on Tegra210 or earlier and have to provide our own in tegra_sor_probe()
3894 sor->clk_pad = NULL; in tegra_sor_probe()
3902 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3904 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); in tegra_sor_probe()
3909 pm_runtime_enable(&pdev->dev); in tegra_sor_probe()
3911 host1x_client_init(&sor->client); in tegra_sor_probe()
3912 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3913 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3916 * On Tegra210 and earlier, provide our own implementation for the in tegra_sor_probe()
3919 if (!sor->clk_pad) { in tegra_sor_probe()
3922 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", in tegra_sor_probe()
3923 sor->index); in tegra_sor_probe()
3925 err = -ENOMEM; in tegra_sor_probe()
3929 err = host1x_client_resume(&sor->client); in tegra_sor_probe()
3931 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_probe()
3935 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); in tegra_sor_probe()
3936 host1x_client_suspend(&sor->client); in tegra_sor_probe()
3939 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3940 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3941 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3946 err = __host1x_client_register(&sor->client); in tegra_sor_probe()
3948 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_sor_probe()
3956 host1x_client_exit(&sor->client); in tegra_sor_probe()
3957 pm_runtime_disable(&pdev->dev); in tegra_sor_probe()
3959 if (sor->aux) in tegra_sor_probe()
3960 sor->output.ddc = NULL; in tegra_sor_probe()
3962 tegra_output_remove(&sor->output); in tegra_sor_probe()
3964 if (sor->aux) in tegra_sor_probe()
3965 put_device(sor->aux->dev); in tegra_sor_probe()
3974 host1x_client_unregister(&sor->client); in tegra_sor_remove()
3976 pm_runtime_disable(&pdev->dev); in tegra_sor_remove()
3978 if (sor->aux) { in tegra_sor_remove()
3979 put_device(sor->aux->dev); in tegra_sor_remove()
3980 sor->output.ddc = NULL; in tegra_sor_remove()
3983 tegra_output_remove(&sor->output); in tegra_sor_remove()
3991 err = tegra_output_suspend(&sor->output); in tegra_sor_suspend()
3997 if (sor->hdmi_supply) { in tegra_sor_suspend()
3998 err = regulator_disable(sor->hdmi_supply); in tegra_sor_suspend()
4000 tegra_output_resume(&sor->output); in tegra_sor_suspend()
4013 if (sor->hdmi_supply) { in tegra_sor_resume()
4014 err = regulator_enable(sor->hdmi_supply); in tegra_sor_resume()
4019 err = tegra_output_resume(&sor->output); in tegra_sor_resume()
4023 if (sor->hdmi_supply) in tegra_sor_resume()
4024 regulator_disable(sor->hdmi_supply); in tegra_sor_resume()
4038 .name = "tegra-sor",