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/linux/arch/parisc/kernel/
H A Dperf_asm.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /* low-level asm for "intrigue" (PA8500-8700 CPU perf counters)
5 * Copyright (C) 2001 Randolph Chung <tausq at parisc-linux.org>
6 * Copyright (C) 2001 Hewlett-Packard (Grant Grundler)
46 sync ; follow ERS
100 ;* %r24 - original DR2 value
101 ;* %r1 - scratch
102 ;* %r29 - scratch
117 ; NOTE: The PCX-W ERS states that DR2_SLOW_RET must be set before any
132 ; Cacheline start (32-byte cacheline)
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/linux/drivers/tty/serial/
H A Dip22zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
32 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
38 /* Write Register 0 */
69 /* Write Register 1 */
85 /* Write Register #2 (Interrupt Vector) */
87 /* Write Register 3 */
90 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
101 /* Write Register 4 */
106 #define SYNC_ENAB 0 /* Sync Modes Enable */
111 #define MONSYNC 0 /* 8 Bit Sync character */
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H A Dsunzilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
24 #define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
30 /* Write Register 0 */
61 /* Write Register 1 */
77 /* Write Register #2 (Interrupt Vector) */
79 /* Write Register 3 */
82 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
93 /* Write Register 4 */
98 #define SYNC_ENAB 0 /* Sync Modes Enable */
103 #define MONSYNC 0 /* 8 Bit Sync character */
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H A Dzs.h1 /* SPDX-License-Identifier: GPL-2.0 */
34 u8 regs[ZS_NUM_REGS]; /* Channel write registers. */
38 * Per-SCC state for locking and the interrupt handler.
52 #define ZS_BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
58 /* Write Register 0 (Command) */
89 /* Write Register 1 (Tx/Rx/Ext Int Enable and WAIT/DMA Commands) */
104 /* Write Register 2 (Interrupt Vector) */
106 /* Write Register 3 (Receive Parameters and Control) */
108 #define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
119 /* Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) */
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H A Dpmac_zilog.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 * of "escc" node (ie. ch-a or ch-b)
64 if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A) in pmz_get_port_A()
66 return uap->mate; in pmz_get_port_A()
78 writeb(reg, port->control_reg); in read_zsreg()
79 return readb(port->control_reg); in read_zsreg()
85 writeb(reg, port->control_reg); in write_zsreg()
86 writeb(value, port->control_reg); in write_zsreg()
91 return readb(port->data_reg); in read_zsdata()
96 writeb(data, port->data_reg); in write_zsdata()
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/linux/rust/kernel/
H A Ddebugfs.rs1 // SPDX-License-Identifier: GPL-2.0
12 use crate::sync::Arc;
77 fn create(name: &CStr, parent: Option<&Dir>) -> Self { in create_file()
81 // If the parent couldn't be allocated, just early-return in create_file()
103 ) -> impl PinInit<File<T>, E> + 'a
105 T: Sync + 'static,
119 scope <- scope
132 pub fn new(name: &CStr) -> Sel
216 read_callback_file<'a, T, E: 'a, F>( &'a self, name: &'a CStr, data: impl PinInit<T, E> + 'a, _f: &'static F, ) -> impl PinInit<File<T>, E> + 'a where T: Send + Sync + 'static, F: Fn(&T, &mut fmt::Formatter<'_>) -> fmt::Result + Send + Sync, read_callback_file() argument
269 read_write_callback_file<'a, T, E: 'a, F, W>( &'a self, name: &'a CStr, data: impl PinInit<T, E> + 'a, _f: &'static F, _w: &'static W, ) -> impl PinInit<File<T>, E> + 'a where T: Send + Sync + 'static, F: Fn(&T, &mut fmt::Formatter<'_>) -> fmt::Result + Send + Sync, W: Fn(&T, &mut UserSliceReader) -> Result + Send + Sync, read_write_callback_file() argument
270 read_write_callback_file<'a, T, E: 'a, F, W>( &'a self, name: &'a CStr, data: impl PinInit<T, E> + 'a, _f: &'static F, _w: &'static W, ) -> impl PinInit<File<T>, E> + 'a where T: Send + Sync + 'static, F: Fn(&T, &mut fmt::Formatter<'_>) -> fmt::Result + Send + Sync, W: Fn(&T, &mut UserSliceReader) -> Result + Send + Sync, read_write_callback_file() argument
325 write_callback_file<'a, T, E: 'a, W>( &'a self, name: &'a CStr, data: impl PinInit<T, E> + 'a, _w: &'static W, ) -> impl PinInit<File<T>, E> + 'a where T: Send + Sync + 'static, W: Fn(&T, &mut UserSliceReader) -> Result + Send + Sync, write_callback_file() argument
561 read_callback_file<T, F>(&self, name: &CStr, data: &'data T, _f: &'static F) where T: Send + Sync + 'static, F: Fn(&T, &mut fmt::Formatter<'_>) -> fmt::Result + Send + Sync, read_callback_file() argument
618 read_write_callback_file<T, F, W>( &self, name: &CStr, data: &'data T, _f: &'static F, _w: &'static W, ) where T: Send + Sync + 'static, F: Fn(&T, &mut fmt::Formatter<'_>) -> fmt::Result + Send + Sync, W: Fn(&T, &mut UserSliceReader) -> Result + Send + Sync, read_write_callback_file() argument
619 read_write_callback_file<T, F, W>( &self, name: &CStr, data: &'data T, _f: &'static F, _w: &'static W, ) where T: Send + Sync + 'static, F: Fn(&T, &mut fmt::Formatter<'_>) -> fmt::Result + Send + Sync, W: Fn(&T, &mut UserSliceReader) -> Result + Send + Sync, read_write_callback_file() argument
666 write_only_callback_file<T, W>(&self, name: &CStr, data: &'data T, _w: &'static W) where T: Send + Sync + 'static, W: Fn(&T, &mut UserSliceReader) -> Result + Send + Sync, write_only_callback_file() argument
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/linux/Documentation/sound/cards/
H A Dhdspm.rst2 Software Interface ALSA-DSP MADI Driver
5 (translated from German, so no good English ;-),
7 2004 - winfried ritsch
11 the Controls and startup-options are ALSA-Standard and only the
19 ------------------
21 * number of channels -- depends on transmission mode
29 * Single Speed -- 1..64 channels
37 * Double Speed -- 1..32 channels
40 Note: Choosing the 56-channel mode for
41 transmission/receive-mode , only 28 are transmitted/received
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/linux/include/uapi/linux/
H A Ddma-buf.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
27 * struct dma_buf_sync - Synchronize with CPU access.
30 * possible to guarantee coherency between the CPU-visible map and underlying
36 * with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the
38 * DMA_BUF_SYNC_END and the same read/write flags.
46 * follow-up work is not submitted to GPU or other device driver until
90 * struct dma_buf_export_sync_file - Get a sync_file from a dma-buf
93 * current set of fences on a dma-buf file descriptor as a sync_file. CPU
94 * waits via poll() or other driver-specific mechanisms typically wait on
95 * whatever fences are on the dma-buf at the time the wait begins. This
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/linux/Documentation/admin-guide/cgroup-v1/
H A Dblkio-controller.rst22 -----------------------------
33 mount -t cgroup -o blkio none /sys/fs/cgroup/blkio
98 --------------------------------
106 see Documentation/block/bfq-iosched.rst.
110 weight. For more details, see Documentation/block/bfq-iosched.rst.
152 are further divided by the type of operation - read or write, sync
159 are further divided by the type of operation - read or write, sync
173 the type of operation - read or write, sync or async. First two fields
186 (there might be a time lag here due to re-ordering of requests by the
188 devices too. This time is further divided by the type of operation -
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/linux/tools/testing/selftests/arm64/mte/
H A Dcheck_buffer_fill.c1 // SPDX-License-Identifier: GPL-2.0
17 1, 555, 1033, MT_GRANULE_SIZE - 1, MT_GRANULE_SIZE,
18 /* page size - 1*/ 0, /* page_size */ 0, /* page size + 1 */ 0
80 mte_initialize_current_context(mode, (uintptr_t)ptr, -underflow_range); in check_buffer_underflow_by_byte()
83 for (j = sizes[i] - 1; (j >= -underflow_range) && in check_buffer_underflow_by_byte()
84 (!cur_mte_cxt.fault_valid); j--) { in check_buffer_underflow_by_byte()
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H A Dcheck_user_mem.c1 // SPDX-License-Identifier: GPL-2.0
49 if (fd == -1) in check_usermem_access_fault()
52 if (write(fd, &val, sizeof(val)) != sizeof(val)) in check_usermem_access_fault()
74 tag_len = len - tag_offset; in check_usermem_access_fault()
92 syscall_len = write(fd, ptr + ptroff, size); in check_usermem_access_fault()
114 * Accessing user memory in kernel with invalid tag should fail in sync in check_usermem_access_fault()
142 void format_test_name(char* name, int name_len, int type, int sync, int map, int len, int offset) { in format_test_name() argument
152 test_type = "write"; in format_test_name()
224 int sync = mte_sync[s]; main() local
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/linux/rust/kernel/debugfs/
H A Dfile_ops.rs1 // SPDX-License-Identifier: GPL-2.0
44 const unsafe fn new(operations: bindings::file_operations, mode: u16) -> Self {
55 pub(crate) const fn mode(&self) -> u16 { in adapt()
61 pub(super) const fn adapt(&self) -> &FileOps<T::Inner> {
71 fn deref(&self) -> &Self::Target { in fmt()
79 fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
80 self.0.write(f)
90 /// * `file` must point to a live, not-ye in writer_open()
156 pub(crate) unsafe extern "C" fn write<T: Reader + Sync>( write() function
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/linux/Documentation/driver-api/memory-devices/
H A Dti-gpmc.rst1 .. SPDX-License-Identifier: GPL-2.0
14 * Pseudo-SRAM devices
65 2. sync common
85 4. read async non-muxed
96 5. read sync muxed
107 6. read sync non-muxed
118 7. write async muxed
131 8. write async non-muxed
144 9. write sync muxed
157 10. write sync non-muxed
/linux/drivers/gpu/drm/i915/gt/
H A Dgen6_engine_cs.c1 // SPDX-License-Identifier: MIT
18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
22 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
23 * produced by non-pipelined state commands), software needs to first
24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
27 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
32 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
33 * BEFORE the pipe-control with a post-sync op and no write-cache
41 * - Render Target Cache Flush Enable ([12] of DW1)
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/linux/sound/core/seq/oss/
H A Dseq_oss_writeq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * seq_oss_writeq.c - write queue and sync
22 * create a write queue record
33 q->dp = dp; in snd_seq_oss_writeq_new()
34 q->maxlen = maxlen; in snd_seq_oss_writeq_new()
35 spin_lock_init(&q->sync_lock); in snd_seq_oss_writeq_new()
36 q->sync_event_put = 0; in snd_seq_oss_writeq_new()
37 q->sync_time = 0; in snd_seq_oss_writeq_new()
38 init_waitqueue_head(&q->sync_sleep); in snd_seq_oss_writeq_new()
41 pool.client = dp->cseq; in snd_seq_oss_writeq_new()
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/linux/drivers/rtc/
H A Drtc-ti-k3.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
45 #define K3RTC_MIN_OFFSET (-277761)
49 .name = "peripheral-registers",
106 * struct ti_k3_rtc - Private data for ti-k3-rtc
108 * @sync_timeout_us: data sync timeout period in uSec
128 ret = regmap_field_read(priv->r_fields[f], &val); in k3rtc_field_read()
140 regmap_field_write(priv->r_fields[f], val); in k3rtc_field_write()
144 * k3rtc_fence - Ensure a register sync took place between the two domains
147 * Return: 0 if the sync took place, else returns -ETIMEDOUT
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/linux/drivers/gpu/drm/radeon/
H A Dr600_dma.c43 * r600_dma_get_rptr - get the current read pointer
55 if (rdev->wb.enabled) in r600_dma_get_rptr()
56 rptr = rdev->wb.wb[ring->rptr_offs/4]; in r600_dma_get_rptr()
64 * r600_dma_get_wptr - get the current write pointer
78 * r600_dma_set_wptr - commit the write pointer
83 * Write the wptr back to the hardware (r6xx+).
88 WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); in r600_dma_set_wptr()
92 * r600_dma_stop - stop the async dma engine
96 * Stop the async dma engine (r6xx-evergreen).
102 if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) in r600_dma_stop()
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H A Devergreen_dma.c31 * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
36 * Add a DMA fence packet to the ring to write
38 * an interrupt if needed (evergreen-SI).
43 struct radeon_ring *ring = &rdev->ring[fence->ring]; in evergreen_dma_fence_ring_emit()
44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr; in evergreen_dma_fence_ring_emit()
45 /* write the fence */ in evergreen_dma_fence_ring_emit()
49 radeon_ring_write(ring, fence->seq); in evergreen_dma_fence_ring_emit()
59 * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
69 struct radeon_ring *ring = &rdev->ring[ib->ring]; in evergreen_dma_ring_ib_execute()
71 if (rdev->wb.enabled) { in evergreen_dma_ring_ib_execute()
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/linux/arch/csky/include/asm/
H A Dbarrier.h1 /* SPDX-License-Identifier: GPL-2.0 */
22 * w: write
69 * sync: completion barrier, all sync.xx instructions
71 * made by ld/st instructions before sync.s
72 * sync.s: inherit from sync, but also shareable to other cores
73 * sync.i: inherit from sync, but also flush cpu pipeline
74 * sync.is: the same with sync.i + sync.s
76 #define mb() asm volatile ("sync\n":::"memory")
80 * Using three sync.is to prevent speculative PTW
82 #define sync_is() asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory")
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dti,gpmc-child.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
24 gpmc,sync-clk-ps:
28 # Chip-select signal timings corresponding to GPMC_CONFIG2:
29 gpmc,cs-on-ns:
33 gpmc,cs-rd-off-ns:
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/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains low-level functions for performing various
7 * This file implements the following functions for all no-hash
11 * - tlbil_va
12 * - tlbil_pid
13 * - tlbil_all
14 * - tlbivax_bcast
18 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
29 #include <asm/asm-offsets.h>
32 #include <asm/asm-compat.h>
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/linux/drivers/gpu/drm/sti/
H A Dsti_vtg.c1 // SPDX-License-Identifier: GPL-2.0
74 #define AWG_DELAY_HD (-9)
75 #define AWG_DELAY_ED (-8)
76 #define AWG_DELAY_SD (-7)
154 put_device(&pdev->dev); in of_vtg_find()
161 writel(1, vtg->regs + VTG_DRST_AUTOC); in vtg_reset()
173 u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1); in vtg_set_output_window()
174 u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1); in vtg_set_output_window()
190 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync, in vtg_set_hsync_vsync_pos() argument
198 clocksperline = mode->htotal; in vtg_set_hsync_vsync_pos()
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/linux/arch/mips/include/asm/octeon/
H A Dcvmx-asm.h7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/octeon-model.h>
38 #define CVMX_SYNC asm volatile ("sync" : : : "memory")
52 * We actually use two syncw instructions in a row when we need a write
54 * errata Core-401. This can cause a single syncw to not enforce
61 * Define new sync instructions to be normal SYNC instructions for
69 * Not using a Cavium compiler, always use the slower sync so the
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/linux/drivers/base/regmap/
H A Dregcache.c1 // SPDX-License-Identifier: GPL-2.0
30 if (x->reg > y->reg) in regcache_defaults_cmp()
32 else if (x->reg < y->reg) in regcache_defaults_cmp()
33 return -1; in regcache_defaults_cmp()
51 for (unsigned int i = 0; i < map->num_reg_defaults_raw; i++) in regcache_count_cacheable_registers()
52 if (regmap_readable(map, i * map->reg_stride) && in regcache_count_cacheable_registers()
53 !regmap_volatile(map, i * map->reg_stride)) in regcache_count_cacheable_registers()
65 if (!map->reg_defaults_raw) { in regcache_hw_init()
66 bool cache_bypass = map->cache_bypass; in regcache_hw_init()
67 dev_dbg(map->dev, "No cache defaults, reading back from HW\n"); in regcache_hw_init()
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/linux/arch/powerpc/include/asm/
H A Dcacheflush.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
35 * It just marks the page as not i-cache clean. We do the i-cache
43 if (test_bit(PG_dcache_clean, &folio->flags.f)) in flush_dcache_folio()
44 clear_bit(PG_dcache_clean, &folio->flags.f); in flush_dcache_folio()
63 * flush_dcache_range(): Write any modified data cache blocks out to memory and
74 void *addr = (void *)(start & ~(bytes - 1)); in flush_dcache_range()
75 unsigned long size = stop - (unsigned long)addr + (bytes - 1); in flush_dcache_range()
79 mb(); /* sync */ in flush_dcache_range()
83 mb(); /* sync */ in flush_dcache_range()
88 * Write any modified data cache blocks out to memory.
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