1 // SPDX-License-Identifier: GPL-2.0
29 	if (x->reg > y->reg)  in regcache_defaults_cmp()
31 	else if (x->reg < y->reg)  in regcache_defaults_cmp()
32 		return -1;  in regcache_defaults_cmp()
52 	if (!map->num_reg_defaults_raw)  in regcache_hw_init()
53 		return -EINVAL;  in regcache_hw_init()
56 	for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++)  in regcache_hw_init()
57 		if (regmap_readable(map, i * map->reg_stride) &&  in regcache_hw_init()
58 		    !regmap_volatile(map, i * map->reg_stride))  in regcache_hw_init()
63 		map->cache_bypass = true;  in regcache_hw_init()
67 	map->num_reg_defaults = count;  in regcache_hw_init()
68 	map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default),  in regcache_hw_init()
70 	if (!map->reg_defaults)  in regcache_hw_init()
71 		return -ENOMEM;  in regcache_hw_init()
73 	if (!map->reg_defaults_raw) {  in regcache_hw_init()
74 		bool cache_bypass = map->cache_bypass;  in regcache_hw_init()
75 		dev_warn(map->dev, "No cache defaults, reading back from HW\n");  in regcache_hw_init()
78 		map->cache_bypass = true;  in regcache_hw_init()
79 		tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);  in regcache_hw_init()
81 			ret = -ENOMEM;  in regcache_hw_init()
85 				      map->cache_size_raw);  in regcache_hw_init()
86 		map->cache_bypass = cache_bypass;  in regcache_hw_init()
88 			map->reg_defaults_raw = tmp_buf;  in regcache_hw_init()
89 			map->cache_free = true;  in regcache_hw_init()
96 	for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {  in regcache_hw_init()
97 		reg = i * map->reg_stride;  in regcache_hw_init()
105 		if (map->reg_defaults_raw) {  in regcache_hw_init()
106 			val = regcache_get_val(map, map->reg_defaults_raw, i);  in regcache_hw_init()
108 			bool cache_bypass = map->cache_bypass;  in regcache_hw_init()
110 			map->cache_bypass = true;  in regcache_hw_init()
112 			map->cache_bypass = cache_bypass;  in regcache_hw_init()
114 				dev_err(map->dev, "Failed to read %d: %d\n",  in regcache_hw_init()
120 		map->reg_defaults[j].reg = reg;  in regcache_hw_init()
121 		map->reg_defaults[j].def = val;  in regcache_hw_init()
128 	kfree(map->reg_defaults);  in regcache_hw_init()
139 	if (map->cache_type == REGCACHE_NONE) {  in regcache_init()
140 		if (config->reg_defaults || config->num_reg_defaults_raw)  in regcache_init()
141 			dev_warn(map->dev,  in regcache_init()
144 		map->cache_bypass = true;  in regcache_init()
148 	if (config->reg_defaults && !config->num_reg_defaults) {  in regcache_init()
149 		dev_err(map->dev,  in regcache_init()
151 		return -EINVAL;  in regcache_init()
154 	if (config->num_reg_defaults && !config->reg_defaults) {  in regcache_init()
155 		dev_err(map->dev,  in regcache_init()
157 		return -EINVAL;  in regcache_init()
160 	for (i = 0; i < config->num_reg_defaults; i++)  in regcache_init()
161 		if (config->reg_defaults[i].reg % map->reg_stride)  in regcache_init()
162 			return -EINVAL;  in regcache_init()
165 		if (cache_types[i]->type == map->cache_type)  in regcache_init()
169 		dev_err(map->dev, "Could not match cache type: %d\n",  in regcache_init()
170 			map->cache_type);  in regcache_init()
171 		return -EINVAL;  in regcache_init()
174 	map->num_reg_defaults = config->num_reg_defaults;  in regcache_init()
175 	map->num_reg_defaults_raw = config->num_reg_defaults_raw;  in regcache_init()
176 	map->reg_defaults_raw = config->reg_defaults_raw;  in regcache_init()
177 	map->cache_word_size = BITS_TO_BYTES(config->val_bits);  in regcache_init()
178 	map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;  in regcache_init()
180 	map->cache = NULL;  in regcache_init()
181 	map->cache_ops = cache_types[i];  in regcache_init()
183 	if (!map->cache_ops->read ||  in regcache_init()
184 	    !map->cache_ops->write ||  in regcache_init()
185 	    !map->cache_ops->name)  in regcache_init()
186 		return -EINVAL;  in regcache_init()
192 	if (config->reg_defaults) {  in regcache_init()
193 		tmp_buf = kmemdup_array(config->reg_defaults, map->num_reg_defaults,  in regcache_init()
194 					sizeof(*map->reg_defaults), GFP_KERNEL);  in regcache_init()
196 			return -ENOMEM;  in regcache_init()
197 		map->reg_defaults = tmp_buf;  in regcache_init()
198 	} else if (map->num_reg_defaults_raw) {  in regcache_init()
206 		if (map->cache_bypass)  in regcache_init()
210 	if (!map->max_register_is_set && map->num_reg_defaults_raw) {  in regcache_init()
211 		map->max_register = (map->num_reg_defaults_raw  - 1) * map->reg_stride;  in regcache_init()
212 		map->max_register_is_set = true;  in regcache_init()
215 	if (map->cache_ops->init) {  in regcache_init()
216 		dev_dbg(map->dev, "Initializing %s cache\n",  in regcache_init()
217 			map->cache_ops->name);  in regcache_init()
218 		map->lock(map->lock_arg);  in regcache_init()
219 		ret = map->cache_ops->init(map);  in regcache_init()
220 		map->unlock(map->lock_arg);  in regcache_init()
227 	kfree(map->reg_defaults);  in regcache_init()
228 	if (map->cache_free)  in regcache_init()
229 		kfree(map->reg_defaults_raw);  in regcache_init()
236 	if (map->cache_type == REGCACHE_NONE)  in regcache_exit()
239 	BUG_ON(!map->cache_ops);  in regcache_exit()
241 	kfree(map->reg_defaults);  in regcache_exit()
242 	if (map->cache_free)  in regcache_exit()
243 		kfree(map->reg_defaults_raw);  in regcache_exit()
245 	if (map->cache_ops->exit) {  in regcache_exit()
246 		dev_dbg(map->dev, "Destroying %s cache\n",  in regcache_exit()
247 			map->cache_ops->name);  in regcache_exit()
248 		map->lock(map->lock_arg);  in regcache_exit()
249 		map->cache_ops->exit(map);  in regcache_exit()
250 		map->unlock(map->lock_arg);  in regcache_exit()
255  * regcache_read - Fetch the value of a given register from the cache.
268 	if (map->cache_type == REGCACHE_NONE)  in regcache_read()
269 		return -EINVAL;  in regcache_read()
271 	BUG_ON(!map->cache_ops);  in regcache_read()
274 		ret = map->cache_ops->read(map, reg, value);  in regcache_read()
282 	return -EINVAL;  in regcache_read()
286  * regcache_write - Set the value of a given register in the cache.
297 	if (map->cache_type == REGCACHE_NONE)  in regcache_write()
300 	BUG_ON(!map->cache_ops);  in regcache_write()
303 		return map->cache_ops->write(map, reg, value);  in regcache_write()
316 	/* If we don't know the chip just got reset, then sync everything. */  in regcache_reg_needs_sync()
317 	if (!map->no_sync_defaults)  in regcache_reg_needs_sync()
322 	if (ret >= 0 && val == map->reg_defaults[ret].def)  in regcache_reg_needs_sync()
332 	for (reg = min; reg <= max; reg += map->reg_stride) {  in regcache_default_sync()
341 		if (ret == -ENOENT)  in regcache_default_sync()
349 		map->cache_bypass = true;  in regcache_default_sync()
351 		map->cache_bypass = false;  in regcache_default_sync()
353 			dev_err(map->dev, "Unable to sync register %#x. %d\n",  in regcache_default_sync()
357 		dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);  in regcache_default_sync()
369  * regcache_sync - Sync the register cache with the hardware.
387 	if (WARN_ON(map->cache_type == REGCACHE_NONE))  in regcache_sync()
388 		return -EINVAL;  in regcache_sync()
390 	BUG_ON(!map->cache_ops);  in regcache_sync()
392 	map->lock(map->lock_arg);  in regcache_sync()
394 	bypass = map->cache_bypass;  in regcache_sync()
395 	dev_dbg(map->dev, "Syncing %s cache\n",  in regcache_sync()
396 		map->cache_ops->name);  in regcache_sync()
397 	name = map->cache_ops->name;  in regcache_sync()
400 	if (!map->cache_dirty)  in regcache_sync()
404 	map->cache_bypass = true;  in regcache_sync()
405 	for (i = 0; i < map->patch_regs; i++) {  in regcache_sync()
406 		ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);  in regcache_sync()
408 			dev_err(map->dev, "Failed to write %x = %x: %d\n",  in regcache_sync()
409 				map->patch[i].reg, map->patch[i].def, ret);  in regcache_sync()
413 	map->cache_bypass = false;  in regcache_sync()
415 	if (map->cache_ops->sync)  in regcache_sync()
416 		ret = map->cache_ops->sync(map, 0, map->max_register);  in regcache_sync()
418 		ret = regcache_default_sync(map, 0, map->max_register);  in regcache_sync()
421 		map->cache_dirty = false;  in regcache_sync()
425 	map->cache_bypass = bypass;  in regcache_sync()
426 	map->no_sync_defaults = false;  in regcache_sync()
431 	 * have gone out of sync, force writes of all the paging  in regcache_sync()
434 	rb_for_each(node, NULL, &map->range_tree, rbtree_all) {  in regcache_sync()
438 		/* If there's nothing in the cache there's nothing to sync */  in regcache_sync()
439 		if (regcache_read(map, this->selector_reg, &i) != 0)  in regcache_sync()
442 		ret = _regmap_write(map, this->selector_reg, i);  in regcache_sync()
444 			dev_err(map->dev, "Failed to write %x = %x: %d\n",  in regcache_sync()
445 				this->selector_reg, i, ret);  in regcache_sync()
450 	map->unlock(map->lock_arg);  in regcache_sync()
461  * regcache_sync_region - Sync part  of the register cache with the hardware.
463  * @map: map to sync.
464  * @min: first register to sync
465  * @max: last register to sync
467  * Write all non-default register values in the specified region to
479 	if (WARN_ON(map->cache_type == REGCACHE_NONE))  in regcache_sync_region()
480 		return -EINVAL;  in regcache_sync_region()
482 	BUG_ON(!map->cache_ops);  in regcache_sync_region()
484 	map->lock(map->lock_arg);  in regcache_sync_region()
487 	bypass = map->cache_bypass;  in regcache_sync_region()
489 	name = map->cache_ops->name;  in regcache_sync_region()
490 	dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max);  in regcache_sync_region()
494 	if (!map->cache_dirty)  in regcache_sync_region()
497 	map->async = true;  in regcache_sync_region()
499 	if (map->cache_ops->sync)  in regcache_sync_region()
500 		ret = map->cache_ops->sync(map, min, max);  in regcache_sync_region()
506 	map->cache_bypass = bypass;  in regcache_sync_region()
507 	map->async = false;  in regcache_sync_region()
508 	map->no_sync_defaults = false;  in regcache_sync_region()
509 	map->unlock(map->lock_arg);  in regcache_sync_region()
520  * regcache_drop_region - Discard part of the register cache
535 	if (!map->cache_ops || !map->cache_ops->drop)  in regcache_drop_region()
536 		return -EINVAL;  in regcache_drop_region()
538 	map->lock(map->lock_arg);  in regcache_drop_region()
542 	ret = map->cache_ops->drop(map, min, max);  in regcache_drop_region()
544 	map->unlock(map->lock_arg);  in regcache_drop_region()
551  * regcache_cache_only - Put a register map into cache only mode
564 	map->lock(map->lock_arg);  in regcache_cache_only()
565 	WARN_ON(map->cache_type != REGCACHE_NONE &&  in regcache_cache_only()
566 		map->cache_bypass && enable);  in regcache_cache_only()
567 	map->cache_only = enable;  in regcache_cache_only()
569 	map->unlock(map->lock_arg);  in regcache_cache_only()
574  * regcache_mark_dirty - Indicate that HW registers were reset to default values
579  * on resume, regcache_sync() knows to write out all non-default values
588 	map->lock(map->lock_arg);  in regcache_mark_dirty()
589 	map->cache_dirty = true;  in regcache_mark_dirty()
590 	map->no_sync_defaults = true;  in regcache_mark_dirty()
591 	map->unlock(map->lock_arg);  in regcache_mark_dirty()
596  * regcache_cache_bypass - Put a register map into cache bypass mode
608 	map->lock(map->lock_arg);  in regcache_cache_bypass()
609 	WARN_ON(map->cache_only && enable);  in regcache_cache_bypass()
610 	map->cache_bypass = enable;  in regcache_cache_bypass()
612 	map->unlock(map->lock_arg);  in regcache_cache_bypass()
617  * regcache_reg_cached - Check if a register is cached
629 	map->lock(map->lock_arg);  in regcache_reg_cached()
633 	map->unlock(map->lock_arg);  in regcache_reg_cached()
643 	if (map->format.format_val) {  in regcache_set_val()
644 		map->format.format_val(base + (map->cache_word_size * idx),  in regcache_set_val()
649 	switch (map->cache_word_size) {  in regcache_set_val()
677 		return -EINVAL;  in regcache_get_val()
680 	if (map->format.parse_val)  in regcache_get_val()
681 		return map->format.parse_val(regcache_get_val_addr(map, base,  in regcache_get_val()
684 	switch (map->cache_word_size) {  in regcache_get_val()
704 	return -1;  in regcache_get_val()
712 	return _a->reg - _b->reg;  in regcache_default_cmp()
723 	r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,  in regcache_lookup_reg()
727 		return r - map->reg_defaults;  in regcache_lookup_reg()
729 		return -ENOENT;  in regcache_lookup_reg()
747 	map->cache_bypass = true;  in regcache_sync_val()
751 	map->cache_bypass = false;  in regcache_sync_val()
754 		dev_err(map->dev, "Unable to sync register %#x. %d\n",  in regcache_sync_val()
758 	dev_dbg(map->dev, "Synced register %#x, value %#x\n",  in regcache_sync_val()
773 		regtmp = block_base + (i * map->reg_stride);  in regcache_sync_block_single()
791 	size_t val_bytes = map->format.val_bytes;  in regcache_sync_block_raw_flush()
797 	count = (cur - base) / map->reg_stride;  in regcache_sync_block_raw_flush()
799 	dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",  in regcache_sync_block_raw_flush()
800 		count * val_bytes, count, base, cur - map->reg_stride);  in regcache_sync_block_raw_flush()
802 	map->cache_bypass = true;  in regcache_sync_block_raw_flush()
806 		dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",  in regcache_sync_block_raw_flush()
807 			base, cur - map->reg_stride, ret);  in regcache_sync_block_raw_flush()
809 	map->cache_bypass = false;  in regcache_sync_block_raw_flush()
828 		regtmp = block_base + (i * map->reg_stride);  in regcache_sync_block_raw()
855 			map->reg_stride);  in regcache_sync_block_raw()
863 	if (regmap_can_raw_write(map) && !map->use_single_write)  in regcache_sync_block()