100a9730eSGuo Ren /* SPDX-License-Identifier: GPL-2.0 */ 200a9730eSGuo Ren 300a9730eSGuo Ren #ifndef __ASM_CSKY_BARRIER_H 400a9730eSGuo Ren #define __ASM_CSKY_BARRIER_H 500a9730eSGuo Ren 600a9730eSGuo Ren #ifndef __ASSEMBLY__ 700a9730eSGuo Ren 800a9730eSGuo Ren #define nop() asm volatile ("nop\n":::"memory") 900a9730eSGuo Ren 108d11f21aSGuo Ren #ifdef CONFIG_SMP 118d11f21aSGuo Ren 128d11f21aSGuo Ren /* 138d11f21aSGuo Ren * bar.brwarws: ordering barrier for all load/store instructions 148d11f21aSGuo Ren * before/after 158d11f21aSGuo Ren * 168d11f21aSGuo Ren * |31|30 26|25 21|20 16|15 10|9 5|4 0| 178d11f21aSGuo Ren * 1 10000 00000 00000 100001 00001 0 bw br aw ar 188d11f21aSGuo Ren * 198d11f21aSGuo Ren * b: before 208d11f21aSGuo Ren * a: after 218d11f21aSGuo Ren * r: read 228d11f21aSGuo Ren * w: write 238d11f21aSGuo Ren * 248d11f21aSGuo Ren * Here are all combinations: 258d11f21aSGuo Ren * 268d11f21aSGuo Ren * bar.brw 278d11f21aSGuo Ren * bar.br 288d11f21aSGuo Ren * bar.bw 298d11f21aSGuo Ren * bar.arw 308d11f21aSGuo Ren * bar.ar 318d11f21aSGuo Ren * bar.aw 328d11f21aSGuo Ren * bar.brwarw 338d11f21aSGuo Ren * bar.brarw 348d11f21aSGuo Ren * bar.bwarw 358d11f21aSGuo Ren * bar.brwar 368d11f21aSGuo Ren * bar.brwaw 378d11f21aSGuo Ren * bar.brar 388d11f21aSGuo Ren * bar.bwaw 398d11f21aSGuo Ren */ 40*186f69b6SGuo Ren #define FULL_FENCE ".long 0x842fc000\n" 41*186f69b6SGuo Ren #define ACQUIRE_FENCE ".long 0x8427c000\n" 42*186f69b6SGuo Ren #define RELEASE_FENCE ".long 0x842ec000\n" 43*186f69b6SGuo Ren 448d11f21aSGuo Ren #define __bar_brw() asm volatile (".long 0x842cc000\n":::"memory") 458d11f21aSGuo Ren #define __bar_br() asm volatile (".long 0x8424c000\n":::"memory") 468d11f21aSGuo Ren #define __bar_bw() asm volatile (".long 0x8428c000\n":::"memory") 478d11f21aSGuo Ren #define __bar_arw() asm volatile (".long 0x8423c000\n":::"memory") 488d11f21aSGuo Ren #define __bar_ar() asm volatile (".long 0x8421c000\n":::"memory") 498d11f21aSGuo Ren #define __bar_aw() asm volatile (".long 0x8422c000\n":::"memory") 50*186f69b6SGuo Ren #define __bar_brwarw() asm volatile (FULL_FENCE:::"memory") 51*186f69b6SGuo Ren #define __bar_brarw() asm volatile (ACQUIRE_FENCE:::"memory") 528d11f21aSGuo Ren #define __bar_bwarw() asm volatile (".long 0x842bc000\n":::"memory") 538d11f21aSGuo Ren #define __bar_brwar() asm volatile (".long 0x842dc000\n":::"memory") 54*186f69b6SGuo Ren #define __bar_brwaw() asm volatile (RELEASE_FENCE:::"memory") 558d11f21aSGuo Ren #define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory") 568d11f21aSGuo Ren #define __bar_brar() asm volatile (".long 0x8425c000\n":::"memory") 578d11f21aSGuo Ren #define __bar_bwaw() asm volatile (".long 0x842ac000\n":::"memory") 588d11f21aSGuo Ren 598d11f21aSGuo Ren #define __smp_mb() __bar_brwarw() 608d11f21aSGuo Ren #define __smp_rmb() __bar_brar() 618d11f21aSGuo Ren #define __smp_wmb() __bar_bwaw() 628d11f21aSGuo Ren 638d11f21aSGuo Ren #define __smp_acquire_fence() __bar_brarw() 648d11f21aSGuo Ren #define __smp_release_fence() __bar_brwaw() 658d11f21aSGuo Ren 668d11f21aSGuo Ren #endif /* CONFIG_SMP */ 678d11f21aSGuo Ren 6800a9730eSGuo Ren /* 6981b23ba6SGuo Ren * sync: completion barrier, all sync.xx instructions 700b1f557aSJunlin Yang * guarantee the last response received by bus transaction 7181b23ba6SGuo Ren * made by ld/st instructions before sync.s 7281b23ba6SGuo Ren * sync.s: inherit from sync, but also shareable to other cores 7381b23ba6SGuo Ren * sync.i: inherit from sync, but also flush cpu pipeline 7481b23ba6SGuo Ren * sync.is: the same with sync.i + sync.s 7500a9730eSGuo Ren */ 768d11f21aSGuo Ren #define mb() asm volatile ("sync\n":::"memory") 7700a9730eSGuo Ren 7800a9730eSGuo Ren #ifdef CONFIG_CPU_HAS_CACHEV2 798d11f21aSGuo Ren /* 808d11f21aSGuo Ren * Using three sync.is to prevent speculative PTW 818d11f21aSGuo Ren */ 828d11f21aSGuo Ren #define sync_is() asm volatile ("sync.is\nsync.is\nsync.is\n":::"memory") 8300a9730eSGuo Ren #endif 8400a9730eSGuo Ren 8500a9730eSGuo Ren #include <asm-generic/barrier.h> 8600a9730eSGuo Ren 8700a9730eSGuo Ren #endif /* __ASSEMBLY__ */ 8800a9730eSGuo Ren #endif /* __ASM_CSKY_BARRIER_H */ 89