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/linux/Documentation/networking/dsa/
H A Dsja1105.rst2 NXP SJA1105 switch driver
8 The NXP SJA1105 is a family of 10 SPI-managed automotive switches:
10 - SJA1105E: First generation, no TTEthernet
11 - SJA1105T: First generation, TTEthernet
12 - SJA1105P: Second generation, no TTEthernet, no SGMII
13 - SJA1105Q: Second generation, TTEthernet, no SGMII
14 - SJA1105R: Second generation, no TTEthernet, SGMII
15 - SJA1105S: Second generation, TTEthernet, SGMII
16 - SJA1110A: Third generation, TTEthernet, SGMII, integrated 100base-T1 and
17 100base-TX PHYs
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/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Lan966x Ethernet switch controller
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
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H A Dxlnx,axi-ethernet.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
35 axistream-connected is specified, in which case the reg
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/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-ipq806x.c36 #define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x) argument
37 #define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2)) argument
38 #define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2)) argument
39 #define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x) argument
40 #define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x) argument
43 #define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8) argument
47 #define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x) argument
50 * MAC1: QSGMII=0 SGMII=0 RGMII=1
51 * MAC2 & MAC3: QSGMII=0 SGMII=1
53 #define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1 argument
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/linux/drivers/net/pcs/
H A Dpcs-mtk-lynxi.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018-2019 MediaTek Inc.
3 /* A library for MediaTek SGMII circuit
13 #include <linux/pcs/pcs-mtk-lynxi.h>
17 /* SGMII subsystem config registers */
50 /* Register to reset SGMII design */
54 /* Register to set SGMII speed, ANA RG_ Control Signals III */
68 /* struct mtk_pcs_lynxi - This structure holds each sgmii regmap andassociated
71 * SGMII modes
94 switch (interface) { in mtk_pcs_lynxi_inband_caps()
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H A Dpcs-xpcs.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/pcs/pcs-xpcs.h>
17 #include "pcs-xpcs.h"
128 for (compat = xpcs->desc->compat; compat->supported; compat++) in xpcs_find_compat()
129 if (compat->interface == interface) in xpcs_find_compat()
137 return &xpcs->pcs; in xpcs_to_phylink_pcs()
147 return -ENODEV; in xpcs_get_an_mode()
149 return compat->an_mode; in xpcs_get_an_mode()
158 for (i = 0; compat->supported[i] != __ETHTOOL_LINK_MODE_MASK_NBITS; i++) in __xpcs_linkmode_supported()
159 if (compat->supported[i] == linkmode) in __xpcs_linkmode_supported()
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/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c7 * Copyright (C) 2003-2018 Cavium, Inc.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Functions for SGMII initialization, configuration,
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-helper.h>
38 #include <asm/octeon/cvmx-helper-board.h>
40 #include <asm/octeon/cvmx-gmxx-defs.h>
41 #include <asm/octeon/cvmx-pcsx-defs.h>
42 #include <asm/octeon/cvmx-pcsxx-defs.h>
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/linux/drivers/net/ethernet/qualcomm/emac/
H A Demac-sgmii.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
5 /* Qualcomm Technologies, Inc. EMAC SGMII Controller driver.
15 #include "emac-mac.h"
16 #include "emac-sgmii.h"
52 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->init)) in emac_sgmii_init()
55 return adpt->phy.sgmii_ops->init(adpt); in emac_sgmii_init()
60 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->open)) in emac_sgmii_open()
63 return adpt->phy.sgmii_ops->open(adpt); in emac_sgmii_open()
68 if (!(adpt->phy.sgmii_ops && adpt->phy.sgmii_ops->close)) in emac_sgmii_close()
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/linux/drivers/net/ethernet/ti/
H A Dnetcp_sgmii.c1 // SPDX-License-Identifier: GPL-2.0
7 * Sandeep Paulraj <s-paulraj@ti.com>
8 * Wingman Kwok <w-kwok2@ti.com>
22 #define SGMII23_OFFSET(x) ((x - 2) * 0x100) argument
23 #define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x))) argument
25 /* SGMII registers */
26 #define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004) argument
27 #define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010) argument
28 #define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014) argument
29 #define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018) argument
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/linux/drivers/net/dsa/b53/
H A Db53_serdes.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Northstar Plus switch SerDes/SGMII PHY main logic
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
73 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_config()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config()
91 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_an_restart()
92 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_an_restart()
105 struct b53_device *dev = pcs_to_b53_pcs(pcs)->dev; in b53_serdes_get_state()
106 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_get_state()
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H A Db53_serdes.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Northstar Plus switch SerDes/SGMII PHY definitions
11 /* Non-standard page used to access SerDes PHY registers on NorthStar Plus */
22 #define B53_SERDES_MII_REG(x) (0x20 + (x) * 2) argument
23 #define B53_SERDES_DIGITAL_CONTROL(x) (0x1e + (x) * 2) argument
104 if (!dev->ops->serdes_map_lane) in b53_serdes_map_lane()
107 return dev->ops->serdes_map_lane(dev, port); in b53_serdes_map_lane()
122 return -ENODEV; in b53_serdes_init()
/linux/drivers/net/phy/
H A Dmxl-gpy.c1 // SPDX-License-Identifier: GPL-2.0+
53 #define PHY_IMASK_WOL BIT(15) /* Wake-on-LAN */
54 #define PHY_IMASK_ANC BIT(10) /* Auto-Neg complete */
55 #define PHY_IMASK_ADSC BIT(5) /* Link auto-downspeed detect */
98 /* SGMII */
135 /* It takes 3 seconds to fully switch out of loopback mode before
136 * it can safely re-enter loopback mode. Record the time when
156 * T = -2.5761e-11*(N^4) + 9.7332e-8*(N^3) + -1.9165e-4*(N^2) +
157 * 3.0762e-1*(N^1) + -5.2156e1
159 * where [-52.156, 137.961]C and N = [0, 1023].
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H A Dbcm54140.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
14 #include "bcm-phy-lib.h"
16 /* RDB per-port registers
61 #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
62 #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
81 * T = 413.35 - (0.49055 * bits[9:0])
83 #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
84 #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
120 * pin choses between 4x SGMII and QSGMII mode:
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
40 Adds support for a set of LED trigger events per-PHY. Link
44 logical-or of all the link speed ones.
69 Currently tested with mpc866ads and mpc8349e-mitx.
121 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
122 - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
130 - ADIN1100 - Robust,Industrial, Low Power 10BASE-T1L Ethernet PHY
144 Currently supports the Asix Electronics PHY found in the X-Surf 100
153 found in the X-Surf 100 AX88796B package.
170 Support the Broadcom BCM54140 Quad SGMII/QSGMII PHY.
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/linux/Documentation/devicetree/bindings/net/dsa/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Ocelot Switch Family
10 - Vladimir Oltean <vladimir.oltean@nxp.com>
11 - Claudiu Manoil <claudiu.manoil@nxp.com>
12 - Alexandre Belloni <alexandre.belloni@bootlin.com>
13 - UNGLinuxDriver@microchip.com
16 There are multiple switches which are either part of the Ocelot-1 family, or
20 them performs packet I/O primarily through an Ethernet port of the switch
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H A Dmediatek,mt7530.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
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/linux/Documentation/ABI/testing/
H A Dsysfs-class-net-phydev24 This attribute contains the 32-bit PHY Identifier as reported
34 This attribute contains the 32-bit PHY Identifier as reported
51 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
52 rmii, rgmii, rgmii-id, rgmii-rxid, rgmii-txid, rtbi, smii
53 xgmii, moca, qsgmii, trgmii, 1000base-x, 2500base-x, rxaui,
54 xaui, 10gbase-kr, unknown
70 32-bit hexadecimal number representing a bit mask of the
72 (Ethernet MAC, switch, etc.) to the PHY driver. The flags are
/linux/arch/arm/boot/dts/marvell/
H A Darmada-385-clearfog-gtr-l8.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 #include "armada-385-clearfog-gtr.dtsi"
7 compatible = "solidrun,clearfog-gtr-l8", "marvell,armada385",
11 sfp1: sfp-1 {
13 pinctrl-0 = <&cf_gtr_sfp1_pins>;
14 pinctrl-names = "default";
15 i2c-bus = <&i2c0>;
16 mod-def0-gpio = <&gpio0 24 GPIO_ACTIVE_LOW>;
17 tx-disable-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
22 switch0: ethernet-switch@4 {
[all …]
H A Darmada-385-clearfog-gtr.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
11 1. 6141 switch (2.5Gbps capable)
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
15 5. SFP connector, or optionally SGMII Ethernet 1512 PHY
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
35 d-cache-size = <0x8000>; // L1, 32K
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-xsphy.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
21 #include "phy-mtk-io.h"
86 /* PHY switch between pcie/usb3/sgmii */
124 void __iomem *pbase = inst->port_base; in u2_phy_slew_rate_calibrate()
130 if (inst->eye_src) in u2_phy_slew_rate_calibrate()
160 /* (1024 / FM_OUT) x reference clock frequency x coefficient */ in u2_phy_slew_rate_calibrate()
161 tmp = xsphy->src_ref_clk * xsphy->src_coef; in u2_phy_slew_rate_calibrate()
168 dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", in u2_phy_slew_rate_calibrate()
169 inst->index, fm_out, calib_val, in u2_phy_slew_rate_calibrate()
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 // Copyright 2020-2021 NXP
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
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/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_port.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
37 switch (lp_abil & LPA_SGMII_SPD_MASK) { in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
[all …]
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-3720-turris-mox.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/bus/moxtet.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include "armada-372x.dtsi"
16 compatible = "cznic,turris-mox", "marvell,armada3720",
28 stdout-path = "serial0:115200n8";
37 compatible = "gpio-leds";
41 linux,default-trigger = "default-on";
[all …]
/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.c1 /* SPDX-License-Identifier: GPL-2.0+ */
42 netif_err(adapter, drv, adapter->netdev, in pci11x1x_strap_get_status()
55 adapter->is_sgmii_en = true; in pci11x1x_strap_get_status()
57 adapter->is_sgmii_en = false; in pci11x1x_strap_get_status()
62 adapter->is_sgmii_en = true; in pci11x1x_strap_get_status()
64 adapter->is_sgmii_en = false; in pci11x1x_strap_get_status()
66 adapter->is_sgmii_en = false; in pci11x1x_strap_get_status()
69 netif_dbg(adapter, drv, adapter->netdev, in pci11x1x_strap_get_status()
70 "SGMII I/F %sable\n", adapter->is_sgmii_en ? "En" : "Dis"); in pci11x1x_strap_get_status()
75 struct lan743x_csr *csr = &adapter->csr; in is_pci11x1x_chip()
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