16937602eSMichael Walle // SPDX-License-Identifier: GPL-2.0+
26937602eSMichael Walle /* Broadcom BCM54140 Quad SGMII/QSGMII Copper/Fiber Gigabit PHY
36937602eSMichael Walle *
46937602eSMichael Walle * Copyright (c) 2020 Michael Walle <michael@walle.cc>
56937602eSMichael Walle */
66937602eSMichael Walle
76937602eSMichael Walle #include <linux/bitfield.h>
86937602eSMichael Walle #include <linux/brcmphy.h>
94406d36dSMichael Walle #include <linux/hwmon.h>
106937602eSMichael Walle #include <linux/module.h>
116937602eSMichael Walle #include <linux/phy.h>
126937602eSMichael Walle
136937602eSMichael Walle #include "bcm-phy-lib.h"
146937602eSMichael Walle
156937602eSMichael Walle /* RDB per-port registers
166937602eSMichael Walle */
176937602eSMichael Walle #define BCM54140_RDB_ISR 0x00a /* interrupt status */
186937602eSMichael Walle #define BCM54140_RDB_IMR 0x00b /* interrupt mask */
196937602eSMichael Walle #define BCM54140_RDB_INT_LINK BIT(1) /* link status changed */
206937602eSMichael Walle #define BCM54140_RDB_INT_SPEED BIT(2) /* link speed change */
216937602eSMichael Walle #define BCM54140_RDB_INT_DUPLEX BIT(3) /* duplex mode changed */
226937602eSMichael Walle #define BCM54140_RDB_SPARE1 0x012 /* spare control 1 */
236937602eSMichael Walle #define BCM54140_RDB_SPARE1_LSLM BIT(2) /* link speed LED mode */
246937602eSMichael Walle #define BCM54140_RDB_SPARE2 0x014 /* spare control 2 */
256937602eSMichael Walle #define BCM54140_RDB_SPARE2_WS_RTRY_DIS BIT(8) /* wirespeed retry disable */
266937602eSMichael Walle #define BCM54140_RDB_SPARE2_WS_RTRY_LIMIT GENMASK(4, 2) /* retry limit */
276937602eSMichael Walle #define BCM54140_RDB_SPARE3 0x015 /* spare control 3 */
286937602eSMichael Walle #define BCM54140_RDB_SPARE3_BIT0 BIT(0)
296937602eSMichael Walle #define BCM54140_RDB_LED_CTRL 0x019 /* LED control */
306937602eSMichael Walle #define BCM54140_RDB_LED_CTRL_ACTLINK0 BIT(4)
316937602eSMichael Walle #define BCM54140_RDB_LED_CTRL_ACTLINK1 BIT(8)
326937602eSMichael Walle #define BCM54140_RDB_C_APWR 0x01a /* auto power down control */
336937602eSMichael Walle #define BCM54140_RDB_C_APWR_SINGLE_PULSE BIT(8) /* single pulse */
346937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_DIS 0 /* ADP disable */
356937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_EN 1 /* ADP enable */
366937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_DIS2 2 /* ADP disable */
376937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG 3 /* ADP enable w/ aneg */
386937602eSMichael Walle #define BCM54140_RDB_C_APWR_APD_MODE_MASK GENMASK(6, 5)
396937602eSMichael Walle #define BCM54140_RDB_C_APWR_SLP_TIM_MASK BIT(4)/* sleep timer */
406937602eSMichael Walle #define BCM54140_RDB_C_APWR_SLP_TIM_2_7 0 /* 2.7s */
416937602eSMichael Walle #define BCM54140_RDB_C_APWR_SLP_TIM_5_4 1 /* 5.4s */
426937602eSMichael Walle #define BCM54140_RDB_C_PWR 0x02a /* copper power control */
436937602eSMichael Walle #define BCM54140_RDB_C_PWR_ISOLATE BIT(5) /* super isolate mode */
446937602eSMichael Walle #define BCM54140_RDB_C_MISC_CTRL 0x02f /* misc copper control */
456937602eSMichael Walle #define BCM54140_RDB_C_MISC_CTRL_WS_EN BIT(4) /* wirespeed enable */
466937602eSMichael Walle
476937602eSMichael Walle /* RDB global registers
486937602eSMichael Walle */
496937602eSMichael Walle #define BCM54140_RDB_TOP_IMR 0x82d /* interrupt mask */
506937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT0 BIT(4)
516937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT1 BIT(5)
526937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT2 BIT(6)
536937602eSMichael Walle #define BCM54140_RDB_TOP_IMR_PORT3 BIT(7)
544406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL 0x831 /* monitor control */
554406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_V_MODE BIT(3) /* voltage mode */
564406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_MASK GENMASK(2, 1)
574406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_TEMP 0 /* meassure temperature */
584406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_1V0 1 /* meassure AVDDL 1.0V */
594406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_3V3 2 /* meassure AVDDH 3.3V */
604406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_SEL_RR 3 /* meassure all round-robin */
614406d36dSMichael Walle #define BCM54140_RDB_MON_CTRL_PWR_DOWN BIT(0) /* power-down monitor */
624406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_VAL 0x832 /* temperature value */
634406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_MAX 0x833 /* temperature high thresh */
644406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_MIN 0x834 /* temperature low thresh */
654406d36dSMichael Walle #define BCM54140_RDB_MON_TEMP_DATA_MASK GENMASK(9, 0)
664406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_VAL 0x835 /* AVDDL 1.0V value */
674406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_MAX 0x836 /* AVDDL 1.0V high thresh */
684406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_MIN 0x837 /* AVDDL 1.0V low thresh */
694406d36dSMichael Walle #define BCM54140_RDB_MON_1V0_DATA_MASK GENMASK(10, 0)
704406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_VAL 0x838 /* AVDDH 3.3V value */
714406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_MAX 0x839 /* AVDDH 3.3V high thresh */
724406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_MIN 0x83a /* AVDDH 3.3V low thresh */
734406d36dSMichael Walle #define BCM54140_RDB_MON_3V3_DATA_MASK GENMASK(11, 0)
744406d36dSMichael Walle #define BCM54140_RDB_MON_ISR 0x83b /* interrupt status */
754406d36dSMichael Walle #define BCM54140_RDB_MON_ISR_3V3 BIT(2) /* AVDDH 3.3V alarm */
764406d36dSMichael Walle #define BCM54140_RDB_MON_ISR_1V0 BIT(1) /* AVDDL 1.0V alarm */
774406d36dSMichael Walle #define BCM54140_RDB_MON_ISR_TEMP BIT(0) /* temperature alarm */
784406d36dSMichael Walle
794406d36dSMichael Walle /* According to the datasheet the formula is:
804406d36dSMichael Walle * T = 413.35 - (0.49055 * bits[9:0])
814406d36dSMichael Walle */
824406d36dSMichael Walle #define BCM54140_HWMON_TO_TEMP(v) (413350L - (v) * 491)
834406d36dSMichael Walle #define BCM54140_HWMON_FROM_TEMP(v) DIV_ROUND_CLOSEST_ULL(413350L - (v), 491)
844406d36dSMichael Walle
854406d36dSMichael Walle /* According to the datasheet the formula is:
864406d36dSMichael Walle * U = bits[11:0] / 1024 * 220 / 0.2
874406d36dSMichael Walle *
884406d36dSMichael Walle * Normalized:
894406d36dSMichael Walle * U = bits[11:0] / 4096 * 2514
904406d36dSMichael Walle */
914406d36dSMichael Walle #define BCM54140_HWMON_TO_IN_1V0(v) ((v) * 2514 >> 11)
924406d36dSMichael Walle #define BCM54140_HWMON_FROM_IN_1V0(v) DIV_ROUND_CLOSEST_ULL(((v) << 11), 2514)
934406d36dSMichael Walle
944406d36dSMichael Walle /* According to the datasheet the formula is:
954406d36dSMichael Walle * U = bits[10:0] / 1024 * 880 / 0.7
964406d36dSMichael Walle *
974406d36dSMichael Walle * Normalized:
984406d36dSMichael Walle * U = bits[10:0] / 2048 * 4400
994406d36dSMichael Walle */
1004406d36dSMichael Walle #define BCM54140_HWMON_TO_IN_3V3(v) ((v) * 4400 >> 12)
1014406d36dSMichael Walle #define BCM54140_HWMON_FROM_IN_3V3(v) DIV_ROUND_CLOSEST_ULL(((v) << 12), 4400)
1024406d36dSMichael Walle
1034406d36dSMichael Walle #define BCM54140_HWMON_TO_IN(ch, v) ((ch) ? BCM54140_HWMON_TO_IN_3V3(v) \
1044406d36dSMichael Walle : BCM54140_HWMON_TO_IN_1V0(v))
1054406d36dSMichael Walle #define BCM54140_HWMON_FROM_IN(ch, v) ((ch) ? BCM54140_HWMON_FROM_IN_3V3(v) \
1064406d36dSMichael Walle : BCM54140_HWMON_FROM_IN_1V0(v))
1074406d36dSMichael Walle #define BCM54140_HWMON_IN_MASK(ch) ((ch) ? BCM54140_RDB_MON_3V3_DATA_MASK \
1084406d36dSMichael Walle : BCM54140_RDB_MON_1V0_DATA_MASK)
1094406d36dSMichael Walle #define BCM54140_HWMON_IN_VAL_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_VAL \
1104406d36dSMichael Walle : BCM54140_RDB_MON_1V0_VAL)
1114406d36dSMichael Walle #define BCM54140_HWMON_IN_MIN_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MIN \
1124406d36dSMichael Walle : BCM54140_RDB_MON_1V0_MIN)
1134406d36dSMichael Walle #define BCM54140_HWMON_IN_MAX_REG(ch) ((ch) ? BCM54140_RDB_MON_3V3_MAX \
1144406d36dSMichael Walle : BCM54140_RDB_MON_1V0_MAX)
1154406d36dSMichael Walle #define BCM54140_HWMON_IN_ALARM_BIT(ch) ((ch) ? BCM54140_RDB_MON_ISR_3V3 \
1164406d36dSMichael Walle : BCM54140_RDB_MON_ISR_1V0)
1176937602eSMichael Walle
118e4e51da6SMichael Walle /* This PHY has two different PHY IDs depening on its MODE_SEL pin. This
119e4e51da6SMichael Walle * pin choses between 4x SGMII and QSGMII mode:
120e4e51da6SMichael Walle * AE02_5009 4x SGMII
121e4e51da6SMichael Walle * AE02_5019 QSGMII
122e4e51da6SMichael Walle */
123e4e51da6SMichael Walle #define BCM54140_PHY_ID_MASK 0xffffffe8
124e4e51da6SMichael Walle
125e9a66851SMichael Walle #define BCM54140_PHY_ID_REV(phy_id) ((phy_id) & 0x7)
126e9a66851SMichael Walle #define BCM54140_REV_B0 1
127e9a66851SMichael Walle
1286937602eSMichael Walle #define BCM54140_DEFAULT_DOWNSHIFT 5
1296937602eSMichael Walle #define BCM54140_MAX_DOWNSHIFT 9
1306937602eSMichael Walle
131*9eea577eSChristian Marangi enum bcm54140_global_phy {
132*9eea577eSChristian Marangi BCM54140_BASE_ADDR = 0,
133*9eea577eSChristian Marangi };
134*9eea577eSChristian Marangi
1356937602eSMichael Walle struct bcm54140_priv {
1366937602eSMichael Walle int port;
1376937602eSMichael Walle int base_addr;
1384406d36dSMichael Walle #if IS_ENABLED(CONFIG_HWMON)
1394406d36dSMichael Walle /* protect the alarm bits */
1404406d36dSMichael Walle struct mutex alarm_lock;
1414406d36dSMichael Walle u16 alarm;
1424406d36dSMichael Walle #endif
1436937602eSMichael Walle };
1446937602eSMichael Walle
1454406d36dSMichael Walle #if IS_ENABLED(CONFIG_HWMON)
bcm54140_hwmon_is_visible(const void * data,enum hwmon_sensor_types type,u32 attr,int channel)1464406d36dSMichael Walle static umode_t bcm54140_hwmon_is_visible(const void *data,
1474406d36dSMichael Walle enum hwmon_sensor_types type,
1484406d36dSMichael Walle u32 attr, int channel)
1494406d36dSMichael Walle {
1504406d36dSMichael Walle switch (type) {
1514406d36dSMichael Walle case hwmon_in:
1524406d36dSMichael Walle switch (attr) {
1534406d36dSMichael Walle case hwmon_in_min:
1544406d36dSMichael Walle case hwmon_in_max:
1554406d36dSMichael Walle return 0644;
1564406d36dSMichael Walle case hwmon_in_label:
1574406d36dSMichael Walle case hwmon_in_input:
1584406d36dSMichael Walle case hwmon_in_alarm:
1594406d36dSMichael Walle return 0444;
1604406d36dSMichael Walle default:
1614406d36dSMichael Walle return 0;
1624406d36dSMichael Walle }
1634406d36dSMichael Walle case hwmon_temp:
1644406d36dSMichael Walle switch (attr) {
1654406d36dSMichael Walle case hwmon_temp_min:
1664406d36dSMichael Walle case hwmon_temp_max:
1674406d36dSMichael Walle return 0644;
1684406d36dSMichael Walle case hwmon_temp_input:
1694406d36dSMichael Walle case hwmon_temp_alarm:
1704406d36dSMichael Walle return 0444;
1714406d36dSMichael Walle default:
1724406d36dSMichael Walle return 0;
1734406d36dSMichael Walle }
1744406d36dSMichael Walle default:
1754406d36dSMichael Walle return 0;
1764406d36dSMichael Walle }
1774406d36dSMichael Walle }
1784406d36dSMichael Walle
bcm54140_hwmon_read_alarm(struct device * dev,unsigned int bit,long * val)1794406d36dSMichael Walle static int bcm54140_hwmon_read_alarm(struct device *dev, unsigned int bit,
1804406d36dSMichael Walle long *val)
1814406d36dSMichael Walle {
1824406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev);
1834406d36dSMichael Walle struct bcm54140_priv *priv = phydev->priv;
1844406d36dSMichael Walle int tmp, ret = 0;
1854406d36dSMichael Walle
1864406d36dSMichael Walle mutex_lock(&priv->alarm_lock);
1874406d36dSMichael Walle
1884406d36dSMichael Walle /* latch any alarm bits */
1894406d36dSMichael Walle tmp = bcm_phy_read_rdb(phydev, BCM54140_RDB_MON_ISR);
1904406d36dSMichael Walle if (tmp < 0) {
1914406d36dSMichael Walle ret = tmp;
1924406d36dSMichael Walle goto out;
1934406d36dSMichael Walle }
1944406d36dSMichael Walle priv->alarm |= tmp;
1954406d36dSMichael Walle
1964406d36dSMichael Walle *val = !!(priv->alarm & bit);
1974406d36dSMichael Walle priv->alarm &= ~bit;
1984406d36dSMichael Walle
1994406d36dSMichael Walle out:
2004406d36dSMichael Walle mutex_unlock(&priv->alarm_lock);
2014406d36dSMichael Walle return ret;
2024406d36dSMichael Walle }
2034406d36dSMichael Walle
bcm54140_hwmon_read_temp(struct device * dev,u32 attr,long * val)2044406d36dSMichael Walle static int bcm54140_hwmon_read_temp(struct device *dev, u32 attr, long *val)
2054406d36dSMichael Walle {
2064406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev);
207efcd549dSColin Ian King u16 reg;
208efcd549dSColin Ian King int tmp;
2094406d36dSMichael Walle
2104406d36dSMichael Walle switch (attr) {
2114406d36dSMichael Walle case hwmon_temp_input:
2124406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_VAL;
2134406d36dSMichael Walle break;
2144406d36dSMichael Walle case hwmon_temp_min:
2154406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MIN;
2164406d36dSMichael Walle break;
2174406d36dSMichael Walle case hwmon_temp_max:
2184406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MAX;
2194406d36dSMichael Walle break;
2204406d36dSMichael Walle case hwmon_temp_alarm:
2214406d36dSMichael Walle return bcm54140_hwmon_read_alarm(dev,
2224406d36dSMichael Walle BCM54140_RDB_MON_ISR_TEMP,
2234406d36dSMichael Walle val);
2244406d36dSMichael Walle default:
2254406d36dSMichael Walle return -EOPNOTSUPP;
2264406d36dSMichael Walle }
2274406d36dSMichael Walle
2284406d36dSMichael Walle tmp = bcm_phy_read_rdb(phydev, reg);
2294406d36dSMichael Walle if (tmp < 0)
2304406d36dSMichael Walle return tmp;
2314406d36dSMichael Walle
2324406d36dSMichael Walle *val = BCM54140_HWMON_TO_TEMP(tmp & BCM54140_RDB_MON_TEMP_DATA_MASK);
2334406d36dSMichael Walle
2344406d36dSMichael Walle return 0;
2354406d36dSMichael Walle }
2364406d36dSMichael Walle
bcm54140_hwmon_read_in(struct device * dev,u32 attr,int channel,long * val)2374406d36dSMichael Walle static int bcm54140_hwmon_read_in(struct device *dev, u32 attr,
2384406d36dSMichael Walle int channel, long *val)
2394406d36dSMichael Walle {
2404406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev);
241efcd549dSColin Ian King u16 bit, reg;
242efcd549dSColin Ian King int tmp;
2434406d36dSMichael Walle
2444406d36dSMichael Walle switch (attr) {
2454406d36dSMichael Walle case hwmon_in_input:
2464406d36dSMichael Walle reg = BCM54140_HWMON_IN_VAL_REG(channel);
2474406d36dSMichael Walle break;
2484406d36dSMichael Walle case hwmon_in_min:
2494406d36dSMichael Walle reg = BCM54140_HWMON_IN_MIN_REG(channel);
2504406d36dSMichael Walle break;
2514406d36dSMichael Walle case hwmon_in_max:
2524406d36dSMichael Walle reg = BCM54140_HWMON_IN_MAX_REG(channel);
2534406d36dSMichael Walle break;
2544406d36dSMichael Walle case hwmon_in_alarm:
2554406d36dSMichael Walle bit = BCM54140_HWMON_IN_ALARM_BIT(channel);
2564406d36dSMichael Walle return bcm54140_hwmon_read_alarm(dev, bit, val);
2574406d36dSMichael Walle default:
2584406d36dSMichael Walle return -EOPNOTSUPP;
2594406d36dSMichael Walle }
2604406d36dSMichael Walle
2614406d36dSMichael Walle tmp = bcm_phy_read_rdb(phydev, reg);
2624406d36dSMichael Walle if (tmp < 0)
2634406d36dSMichael Walle return tmp;
2644406d36dSMichael Walle
2654406d36dSMichael Walle tmp &= BCM54140_HWMON_IN_MASK(channel);
2664406d36dSMichael Walle *val = BCM54140_HWMON_TO_IN(channel, tmp);
2674406d36dSMichael Walle
2684406d36dSMichael Walle return 0;
2694406d36dSMichael Walle }
2704406d36dSMichael Walle
bcm54140_hwmon_read(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long * val)2714406d36dSMichael Walle static int bcm54140_hwmon_read(struct device *dev,
2724406d36dSMichael Walle enum hwmon_sensor_types type, u32 attr,
2734406d36dSMichael Walle int channel, long *val)
2744406d36dSMichael Walle {
2754406d36dSMichael Walle switch (type) {
2764406d36dSMichael Walle case hwmon_temp:
2774406d36dSMichael Walle return bcm54140_hwmon_read_temp(dev, attr, val);
2784406d36dSMichael Walle case hwmon_in:
2794406d36dSMichael Walle return bcm54140_hwmon_read_in(dev, attr, channel, val);
2804406d36dSMichael Walle default:
2814406d36dSMichael Walle return -EOPNOTSUPP;
2824406d36dSMichael Walle }
2834406d36dSMichael Walle }
2844406d36dSMichael Walle
2854406d36dSMichael Walle static const char *const bcm54140_hwmon_in_labels[] = {
2864406d36dSMichael Walle "AVDDL",
2874406d36dSMichael Walle "AVDDH",
2884406d36dSMichael Walle };
2894406d36dSMichael Walle
bcm54140_hwmon_read_string(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,const char ** str)2904406d36dSMichael Walle static int bcm54140_hwmon_read_string(struct device *dev,
2914406d36dSMichael Walle enum hwmon_sensor_types type, u32 attr,
2924406d36dSMichael Walle int channel, const char **str)
2934406d36dSMichael Walle {
2944406d36dSMichael Walle switch (type) {
2954406d36dSMichael Walle case hwmon_in:
2964406d36dSMichael Walle switch (attr) {
2974406d36dSMichael Walle case hwmon_in_label:
2984406d36dSMichael Walle *str = bcm54140_hwmon_in_labels[channel];
2994406d36dSMichael Walle return 0;
3004406d36dSMichael Walle default:
3014406d36dSMichael Walle return -EOPNOTSUPP;
3024406d36dSMichael Walle }
3034406d36dSMichael Walle default:
3044406d36dSMichael Walle return -EOPNOTSUPP;
3054406d36dSMichael Walle }
3064406d36dSMichael Walle }
3074406d36dSMichael Walle
bcm54140_hwmon_write_temp(struct device * dev,u32 attr,int channel,long val)3084406d36dSMichael Walle static int bcm54140_hwmon_write_temp(struct device *dev, u32 attr,
3094406d36dSMichael Walle int channel, long val)
3104406d36dSMichael Walle {
3114406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev);
3124406d36dSMichael Walle u16 mask = BCM54140_RDB_MON_TEMP_DATA_MASK;
3134406d36dSMichael Walle u16 reg;
3144406d36dSMichael Walle
3154406d36dSMichael Walle val = clamp_val(val, BCM54140_HWMON_TO_TEMP(mask),
3164406d36dSMichael Walle BCM54140_HWMON_TO_TEMP(0));
3174406d36dSMichael Walle
3184406d36dSMichael Walle switch (attr) {
3194406d36dSMichael Walle case hwmon_temp_min:
3204406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MIN;
3214406d36dSMichael Walle break;
3224406d36dSMichael Walle case hwmon_temp_max:
3234406d36dSMichael Walle reg = BCM54140_RDB_MON_TEMP_MAX;
3244406d36dSMichael Walle break;
3254406d36dSMichael Walle default:
3264406d36dSMichael Walle return -EOPNOTSUPP;
3274406d36dSMichael Walle }
3284406d36dSMichael Walle
3294406d36dSMichael Walle return bcm_phy_modify_rdb(phydev, reg, mask,
3304406d36dSMichael Walle BCM54140_HWMON_FROM_TEMP(val));
3314406d36dSMichael Walle }
3324406d36dSMichael Walle
bcm54140_hwmon_write_in(struct device * dev,u32 attr,int channel,long val)3334406d36dSMichael Walle static int bcm54140_hwmon_write_in(struct device *dev, u32 attr,
3344406d36dSMichael Walle int channel, long val)
3354406d36dSMichael Walle {
3364406d36dSMichael Walle struct phy_device *phydev = dev_get_drvdata(dev);
3374406d36dSMichael Walle u16 mask = BCM54140_HWMON_IN_MASK(channel);
3384406d36dSMichael Walle u16 reg;
3394406d36dSMichael Walle
3404406d36dSMichael Walle val = clamp_val(val, 0, BCM54140_HWMON_TO_IN(channel, mask));
3414406d36dSMichael Walle
3424406d36dSMichael Walle switch (attr) {
3434406d36dSMichael Walle case hwmon_in_min:
3444406d36dSMichael Walle reg = BCM54140_HWMON_IN_MIN_REG(channel);
3454406d36dSMichael Walle break;
3464406d36dSMichael Walle case hwmon_in_max:
3474406d36dSMichael Walle reg = BCM54140_HWMON_IN_MAX_REG(channel);
3484406d36dSMichael Walle break;
3494406d36dSMichael Walle default:
3504406d36dSMichael Walle return -EOPNOTSUPP;
3514406d36dSMichael Walle }
3524406d36dSMichael Walle
3534406d36dSMichael Walle return bcm_phy_modify_rdb(phydev, reg, mask,
3544406d36dSMichael Walle BCM54140_HWMON_FROM_IN(channel, val));
3554406d36dSMichael Walle }
3564406d36dSMichael Walle
bcm54140_hwmon_write(struct device * dev,enum hwmon_sensor_types type,u32 attr,int channel,long val)3574406d36dSMichael Walle static int bcm54140_hwmon_write(struct device *dev,
3584406d36dSMichael Walle enum hwmon_sensor_types type, u32 attr,
3594406d36dSMichael Walle int channel, long val)
3604406d36dSMichael Walle {
3614406d36dSMichael Walle switch (type) {
3624406d36dSMichael Walle case hwmon_temp:
3634406d36dSMichael Walle return bcm54140_hwmon_write_temp(dev, attr, channel, val);
3644406d36dSMichael Walle case hwmon_in:
3654406d36dSMichael Walle return bcm54140_hwmon_write_in(dev, attr, channel, val);
3664406d36dSMichael Walle default:
3674406d36dSMichael Walle return -EOPNOTSUPP;
3684406d36dSMichael Walle }
3694406d36dSMichael Walle }
3704406d36dSMichael Walle
371211f70beSKrzysztof Kozlowski static const struct hwmon_channel_info * const bcm54140_hwmon_info[] = {
3724406d36dSMichael Walle HWMON_CHANNEL_INFO(temp,
3734406d36dSMichael Walle HWMON_T_INPUT | HWMON_T_MIN | HWMON_T_MAX |
3744406d36dSMichael Walle HWMON_T_ALARM),
3754406d36dSMichael Walle HWMON_CHANNEL_INFO(in,
3764406d36dSMichael Walle HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
3774406d36dSMichael Walle HWMON_I_ALARM | HWMON_I_LABEL,
3784406d36dSMichael Walle HWMON_I_INPUT | HWMON_I_MIN | HWMON_I_MAX |
3794406d36dSMichael Walle HWMON_I_ALARM | HWMON_I_LABEL),
3804406d36dSMichael Walle NULL
3814406d36dSMichael Walle };
3824406d36dSMichael Walle
3834406d36dSMichael Walle static const struct hwmon_ops bcm54140_hwmon_ops = {
3844406d36dSMichael Walle .is_visible = bcm54140_hwmon_is_visible,
3854406d36dSMichael Walle .read = bcm54140_hwmon_read,
3864406d36dSMichael Walle .read_string = bcm54140_hwmon_read_string,
3874406d36dSMichael Walle .write = bcm54140_hwmon_write,
3884406d36dSMichael Walle };
3894406d36dSMichael Walle
3904406d36dSMichael Walle static const struct hwmon_chip_info bcm54140_chip_info = {
3914406d36dSMichael Walle .ops = &bcm54140_hwmon_ops,
3924406d36dSMichael Walle .info = bcm54140_hwmon_info,
3934406d36dSMichael Walle };
3944406d36dSMichael Walle
bcm54140_enable_monitoring(struct phy_device * phydev)3954406d36dSMichael Walle static int bcm54140_enable_monitoring(struct phy_device *phydev)
3964406d36dSMichael Walle {
3974406d36dSMichael Walle u16 mask, set;
3984406d36dSMichael Walle
3994406d36dSMichael Walle /* 3.3V voltage mode */
4004406d36dSMichael Walle set = BCM54140_RDB_MON_CTRL_V_MODE;
4014406d36dSMichael Walle
4024406d36dSMichael Walle /* select round-robin */
4034406d36dSMichael Walle mask = BCM54140_RDB_MON_CTRL_SEL_MASK;
4044406d36dSMichael Walle set |= FIELD_PREP(BCM54140_RDB_MON_CTRL_SEL_MASK,
4054406d36dSMichael Walle BCM54140_RDB_MON_CTRL_SEL_RR);
4064406d36dSMichael Walle
4074406d36dSMichael Walle /* remove power-down bit */
4084406d36dSMichael Walle mask |= BCM54140_RDB_MON_CTRL_PWR_DOWN;
4094406d36dSMichael Walle
4104406d36dSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_MON_CTRL, mask, set);
4114406d36dSMichael Walle }
4124406d36dSMichael Walle
bcm54140_probe_once(struct phy_device * phydev)4134406d36dSMichael Walle static int bcm54140_probe_once(struct phy_device *phydev)
4144406d36dSMichael Walle {
4154406d36dSMichael Walle struct device *hwmon;
4164406d36dSMichael Walle int ret;
4174406d36dSMichael Walle
4184406d36dSMichael Walle /* enable hardware monitoring */
4194406d36dSMichael Walle ret = bcm54140_enable_monitoring(phydev);
4204406d36dSMichael Walle if (ret)
4214406d36dSMichael Walle return ret;
4224406d36dSMichael Walle
4234406d36dSMichael Walle hwmon = devm_hwmon_device_register_with_info(&phydev->mdio.dev,
4244406d36dSMichael Walle "BCM54140", phydev,
4254406d36dSMichael Walle &bcm54140_chip_info,
4264406d36dSMichael Walle NULL);
4274406d36dSMichael Walle return PTR_ERR_OR_ZERO(hwmon);
4284406d36dSMichael Walle }
4294406d36dSMichael Walle #endif
4304406d36dSMichael Walle
bcm54140_base_read_rdb(struct phy_device * phydev,u16 rdb)4316937602eSMichael Walle static int bcm54140_base_read_rdb(struct phy_device *phydev, u16 rdb)
4326937602eSMichael Walle {
4336937602eSMichael Walle int ret;
4346937602eSMichael Walle
435dc9989f1SMichael Walle phy_lock_mdio_bus(phydev);
436*9eea577eSChristian Marangi ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
437*9eea577eSChristian Marangi MII_BCM54XX_RDB_ADDR, rdb);
4386937602eSMichael Walle if (ret < 0)
4396937602eSMichael Walle goto out;
4406937602eSMichael Walle
441*9eea577eSChristian Marangi ret = __phy_package_read(phydev, BCM54140_BASE_ADDR,
442*9eea577eSChristian Marangi MII_BCM54XX_RDB_DATA);
4436937602eSMichael Walle
4446937602eSMichael Walle out:
445dc9989f1SMichael Walle phy_unlock_mdio_bus(phydev);
4466937602eSMichael Walle return ret;
4476937602eSMichael Walle }
4486937602eSMichael Walle
bcm54140_base_write_rdb(struct phy_device * phydev,u16 rdb,u16 val)4496937602eSMichael Walle static int bcm54140_base_write_rdb(struct phy_device *phydev,
4506937602eSMichael Walle u16 rdb, u16 val)
4516937602eSMichael Walle {
4526937602eSMichael Walle int ret;
4536937602eSMichael Walle
454dc9989f1SMichael Walle phy_lock_mdio_bus(phydev);
455*9eea577eSChristian Marangi ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
456*9eea577eSChristian Marangi MII_BCM54XX_RDB_ADDR, rdb);
4576937602eSMichael Walle if (ret < 0)
4586937602eSMichael Walle goto out;
4596937602eSMichael Walle
460*9eea577eSChristian Marangi ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
461*9eea577eSChristian Marangi MII_BCM54XX_RDB_DATA, val);
4626937602eSMichael Walle
4636937602eSMichael Walle out:
464dc9989f1SMichael Walle phy_unlock_mdio_bus(phydev);
4656937602eSMichael Walle return ret;
4666937602eSMichael Walle }
4676937602eSMichael Walle
4686937602eSMichael Walle /* Under some circumstances a core PLL may not lock, this will then prevent
4696937602eSMichael Walle * a successful link establishment. Restart the PLL after the voltages are
4706937602eSMichael Walle * stable to workaround this issue.
4716937602eSMichael Walle */
bcm54140_b0_workaround(struct phy_device * phydev)4726937602eSMichael Walle static int bcm54140_b0_workaround(struct phy_device *phydev)
4736937602eSMichael Walle {
4746937602eSMichael Walle int spare3;
4756937602eSMichael Walle int ret;
4766937602eSMichael Walle
4776937602eSMichael Walle spare3 = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE3);
4786937602eSMichael Walle if (spare3 < 0)
4796937602eSMichael Walle return spare3;
4806937602eSMichael Walle
4816937602eSMichael Walle spare3 &= ~BCM54140_RDB_SPARE3_BIT0;
4826937602eSMichael Walle
4836937602eSMichael Walle ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
4846937602eSMichael Walle if (ret)
4856937602eSMichael Walle return ret;
4866937602eSMichael Walle
4876937602eSMichael Walle ret = phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN);
4886937602eSMichael Walle if (ret)
4896937602eSMichael Walle return ret;
4906937602eSMichael Walle
4916937602eSMichael Walle ret = phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0);
4926937602eSMichael Walle if (ret)
4936937602eSMichael Walle return ret;
4946937602eSMichael Walle
4956937602eSMichael Walle spare3 |= BCM54140_RDB_SPARE3_BIT0;
4966937602eSMichael Walle
4976937602eSMichael Walle return bcm_phy_write_rdb(phydev, BCM54140_RDB_SPARE3, spare3);
4986937602eSMichael Walle }
4996937602eSMichael Walle
5006937602eSMichael Walle /* The BCM54140 is a quad PHY where only the first port has access to the
5016937602eSMichael Walle * global register. Thus we need to find out its PHY address.
5026937602eSMichael Walle *
5036937602eSMichael Walle */
bcm54140_get_base_addr_and_port(struct phy_device * phydev)5046937602eSMichael Walle static int bcm54140_get_base_addr_and_port(struct phy_device *phydev)
5056937602eSMichael Walle {
5066937602eSMichael Walle struct bcm54140_priv *priv = phydev->priv;
5076937602eSMichael Walle struct mii_bus *bus = phydev->mdio.bus;
5086937602eSMichael Walle int addr, min_addr, max_addr;
5096937602eSMichael Walle int step = 1;
5106937602eSMichael Walle u32 phy_id;
5116937602eSMichael Walle int tmp;
5126937602eSMichael Walle
5136937602eSMichael Walle min_addr = phydev->mdio.addr;
5146937602eSMichael Walle max_addr = phydev->mdio.addr;
5156937602eSMichael Walle addr = phydev->mdio.addr;
5166937602eSMichael Walle
5176937602eSMichael Walle /* We scan forward and backwards and look for PHYs which have the
5186937602eSMichael Walle * same phy_id like we do. Step 1 will scan forward, step 2
5196937602eSMichael Walle * backwards. Once we are finished, we have a min_addr and
5206937602eSMichael Walle * max_addr which resembles the range of PHY addresses of the same
5216937602eSMichael Walle * type of PHY. There is one caveat; there may be many PHYs of
5226937602eSMichael Walle * the same type, but we know that each PHY takes exactly 4
5236937602eSMichael Walle * consecutive addresses. Therefore we can deduce our offset
5246937602eSMichael Walle * to the base address of this quad PHY.
5256937602eSMichael Walle */
5266937602eSMichael Walle
5276937602eSMichael Walle while (1) {
5286937602eSMichael Walle if (step == 3) {
5296937602eSMichael Walle break;
5306937602eSMichael Walle } else if (step == 1) {
5316937602eSMichael Walle max_addr = addr;
5326937602eSMichael Walle addr++;
5336937602eSMichael Walle } else {
5346937602eSMichael Walle min_addr = addr;
5356937602eSMichael Walle addr--;
5366937602eSMichael Walle }
5376937602eSMichael Walle
5386937602eSMichael Walle if (addr < 0 || addr >= PHY_MAX_ADDR) {
5396937602eSMichael Walle addr = phydev->mdio.addr;
5406937602eSMichael Walle step++;
5416937602eSMichael Walle continue;
5426937602eSMichael Walle }
5436937602eSMichael Walle
5446937602eSMichael Walle /* read the PHY id */
5456937602eSMichael Walle tmp = mdiobus_read(bus, addr, MII_PHYSID1);
5466937602eSMichael Walle if (tmp < 0)
5476937602eSMichael Walle return tmp;
5486937602eSMichael Walle phy_id = tmp << 16;
5496937602eSMichael Walle tmp = mdiobus_read(bus, addr, MII_PHYSID2);
5506937602eSMichael Walle if (tmp < 0)
5516937602eSMichael Walle return tmp;
5526937602eSMichael Walle phy_id |= tmp;
5536937602eSMichael Walle
5546937602eSMichael Walle /* see if it is still the same PHY */
5556937602eSMichael Walle if ((phy_id & phydev->drv->phy_id_mask) !=
5566937602eSMichael Walle (phydev->drv->phy_id & phydev->drv->phy_id_mask)) {
5576937602eSMichael Walle addr = phydev->mdio.addr;
5586937602eSMichael Walle step++;
5596937602eSMichael Walle }
5606937602eSMichael Walle }
5616937602eSMichael Walle
5626937602eSMichael Walle /* The range we get should be a multiple of four. Please note that both
5636937602eSMichael Walle * the min_addr and max_addr are inclusive. So we have to add one if we
5646937602eSMichael Walle * subtract them.
5656937602eSMichael Walle */
5666937602eSMichael Walle if ((max_addr - min_addr + 1) % 4) {
5676937602eSMichael Walle dev_err(&phydev->mdio.dev,
5686937602eSMichael Walle "Detected Quad PHY IDs %d..%d doesn't make sense.\n",
5696937602eSMichael Walle min_addr, max_addr);
5706937602eSMichael Walle return -EINVAL;
5716937602eSMichael Walle }
5726937602eSMichael Walle
5736937602eSMichael Walle priv->port = (phydev->mdio.addr - min_addr) % 4;
5746937602eSMichael Walle priv->base_addr = phydev->mdio.addr - priv->port;
5756937602eSMichael Walle
5766937602eSMichael Walle return 0;
5776937602eSMichael Walle }
5786937602eSMichael Walle
bcm54140_probe(struct phy_device * phydev)5796937602eSMichael Walle static int bcm54140_probe(struct phy_device *phydev)
5806937602eSMichael Walle {
5816937602eSMichael Walle struct bcm54140_priv *priv;
5826937602eSMichael Walle int ret;
5836937602eSMichael Walle
5846937602eSMichael Walle priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
5856937602eSMichael Walle if (!priv)
5866937602eSMichael Walle return -ENOMEM;
5876937602eSMichael Walle
5886937602eSMichael Walle phydev->priv = priv;
5896937602eSMichael Walle
5906937602eSMichael Walle ret = bcm54140_get_base_addr_and_port(phydev);
5916937602eSMichael Walle if (ret)
5926937602eSMichael Walle return ret;
5936937602eSMichael Walle
594dc9989f1SMichael Walle devm_phy_package_join(&phydev->mdio.dev, phydev, priv->base_addr, 0);
595dc9989f1SMichael Walle
5964406d36dSMichael Walle #if IS_ENABLED(CONFIG_HWMON)
5974406d36dSMichael Walle mutex_init(&priv->alarm_lock);
5984406d36dSMichael Walle
599dc9989f1SMichael Walle if (phy_package_init_once(phydev)) {
6004406d36dSMichael Walle ret = bcm54140_probe_once(phydev);
6014406d36dSMichael Walle if (ret)
6024406d36dSMichael Walle return ret;
6034406d36dSMichael Walle }
6044406d36dSMichael Walle #endif
6054406d36dSMichael Walle
6066937602eSMichael Walle phydev_dbg(phydev, "probed (port %d, base PHY address %d)\n",
6076937602eSMichael Walle priv->port, priv->base_addr);
6086937602eSMichael Walle
6096937602eSMichael Walle return 0;
6106937602eSMichael Walle }
6116937602eSMichael Walle
bcm54140_config_init(struct phy_device * phydev)6126937602eSMichael Walle static int bcm54140_config_init(struct phy_device *phydev)
6136937602eSMichael Walle {
6146937602eSMichael Walle u16 reg = 0xffff;
6156937602eSMichael Walle int ret;
6166937602eSMichael Walle
6176937602eSMichael Walle /* Apply hardware errata */
618e9a66851SMichael Walle if (BCM54140_PHY_ID_REV(phydev->phy_id) == BCM54140_REV_B0) {
6196937602eSMichael Walle ret = bcm54140_b0_workaround(phydev);
6206937602eSMichael Walle if (ret)
6216937602eSMichael Walle return ret;
622e9a66851SMichael Walle }
6236937602eSMichael Walle
6246937602eSMichael Walle /* Unmask events we are interested in. */
6256937602eSMichael Walle reg &= ~(BCM54140_RDB_INT_DUPLEX |
6266937602eSMichael Walle BCM54140_RDB_INT_SPEED |
6276937602eSMichael Walle BCM54140_RDB_INT_LINK);
6286937602eSMichael Walle ret = bcm_phy_write_rdb(phydev, BCM54140_RDB_IMR, reg);
6296937602eSMichael Walle if (ret)
6306937602eSMichael Walle return ret;
6316937602eSMichael Walle
6326937602eSMichael Walle /* LED1=LINKSPD[1], LED2=LINKSPD[2], LED3=LINK/ACTIVITY */
6336937602eSMichael Walle ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE1,
6346937602eSMichael Walle 0, BCM54140_RDB_SPARE1_LSLM);
6356937602eSMichael Walle if (ret)
6366937602eSMichael Walle return ret;
6376937602eSMichael Walle
6386937602eSMichael Walle ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_LED_CTRL,
6396937602eSMichael Walle 0, BCM54140_RDB_LED_CTRL_ACTLINK0);
6406937602eSMichael Walle if (ret)
6416937602eSMichael Walle return ret;
6426937602eSMichael Walle
6436937602eSMichael Walle /* disable super isolate mode */
6446937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_PWR,
6456937602eSMichael Walle BCM54140_RDB_C_PWR_ISOLATE, 0);
6466937602eSMichael Walle }
6476937602eSMichael Walle
bcm54140_handle_interrupt(struct phy_device * phydev)6484567d5c3SIoana Ciornei static irqreturn_t bcm54140_handle_interrupt(struct phy_device *phydev)
6496937602eSMichael Walle {
6504567d5c3SIoana Ciornei int irq_status, irq_mask;
6516937602eSMichael Walle
6524567d5c3SIoana Ciornei irq_status = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
6534567d5c3SIoana Ciornei if (irq_status < 0) {
6544567d5c3SIoana Ciornei phy_error(phydev);
6554567d5c3SIoana Ciornei return IRQ_NONE;
6564567d5c3SIoana Ciornei }
6576937602eSMichael Walle
6584567d5c3SIoana Ciornei irq_mask = bcm_phy_read_rdb(phydev, BCM54140_RDB_IMR);
6594567d5c3SIoana Ciornei if (irq_mask < 0) {
6604567d5c3SIoana Ciornei phy_error(phydev);
6614567d5c3SIoana Ciornei return IRQ_NONE;
6624567d5c3SIoana Ciornei }
6634567d5c3SIoana Ciornei irq_mask = ~irq_mask;
6644567d5c3SIoana Ciornei
6654567d5c3SIoana Ciornei if (!(irq_status & irq_mask))
6664567d5c3SIoana Ciornei return IRQ_NONE;
6674567d5c3SIoana Ciornei
6684567d5c3SIoana Ciornei phy_trigger_machine(phydev);
6694567d5c3SIoana Ciornei
6704567d5c3SIoana Ciornei return IRQ_HANDLED;
6716937602eSMichael Walle }
6726937602eSMichael Walle
bcm54140_ack_intr(struct phy_device * phydev)6739d422050SChenTao static int bcm54140_ack_intr(struct phy_device *phydev)
6746937602eSMichael Walle {
6756937602eSMichael Walle int reg;
6766937602eSMichael Walle
6776937602eSMichael Walle /* clear pending interrupts */
6786937602eSMichael Walle reg = bcm_phy_read_rdb(phydev, BCM54140_RDB_ISR);
6796937602eSMichael Walle if (reg < 0)
6806937602eSMichael Walle return reg;
6816937602eSMichael Walle
6826937602eSMichael Walle return 0;
6836937602eSMichael Walle }
6846937602eSMichael Walle
bcm54140_config_intr(struct phy_device * phydev)6859d422050SChenTao static int bcm54140_config_intr(struct phy_device *phydev)
6866937602eSMichael Walle {
6876937602eSMichael Walle struct bcm54140_priv *priv = phydev->priv;
6886937602eSMichael Walle static const u16 port_to_imr_bit[] = {
6896937602eSMichael Walle BCM54140_RDB_TOP_IMR_PORT0, BCM54140_RDB_TOP_IMR_PORT1,
6906937602eSMichael Walle BCM54140_RDB_TOP_IMR_PORT2, BCM54140_RDB_TOP_IMR_PORT3,
6916937602eSMichael Walle };
69215772e4dSIoana Ciornei int reg, err;
6936937602eSMichael Walle
6946937602eSMichael Walle if (priv->port >= ARRAY_SIZE(port_to_imr_bit))
6956937602eSMichael Walle return -EINVAL;
6966937602eSMichael Walle
6976937602eSMichael Walle reg = bcm54140_base_read_rdb(phydev, BCM54140_RDB_TOP_IMR);
6986937602eSMichael Walle if (reg < 0)
6996937602eSMichael Walle return reg;
7006937602eSMichael Walle
70115772e4dSIoana Ciornei if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
70215772e4dSIoana Ciornei err = bcm54140_ack_intr(phydev);
70315772e4dSIoana Ciornei if (err)
70415772e4dSIoana Ciornei return err;
7056937602eSMichael Walle
70615772e4dSIoana Ciornei reg &= ~port_to_imr_bit[priv->port];
70715772e4dSIoana Ciornei err = bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
70815772e4dSIoana Ciornei } else {
70915772e4dSIoana Ciornei reg |= port_to_imr_bit[priv->port];
71015772e4dSIoana Ciornei err = bcm54140_base_write_rdb(phydev, BCM54140_RDB_TOP_IMR, reg);
71115772e4dSIoana Ciornei if (err)
71215772e4dSIoana Ciornei return err;
71315772e4dSIoana Ciornei
71415772e4dSIoana Ciornei err = bcm54140_ack_intr(phydev);
71515772e4dSIoana Ciornei }
71615772e4dSIoana Ciornei
71715772e4dSIoana Ciornei return err;
7186937602eSMichael Walle }
7196937602eSMichael Walle
bcm54140_get_downshift(struct phy_device * phydev,u8 * data)7206937602eSMichael Walle static int bcm54140_get_downshift(struct phy_device *phydev, u8 *data)
7216937602eSMichael Walle {
7226937602eSMichael Walle int val;
7236937602eSMichael Walle
7246937602eSMichael Walle val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_MISC_CTRL);
7256937602eSMichael Walle if (val < 0)
7266937602eSMichael Walle return val;
7276937602eSMichael Walle
7286937602eSMichael Walle if (!(val & BCM54140_RDB_C_MISC_CTRL_WS_EN)) {
7296937602eSMichael Walle *data = DOWNSHIFT_DEV_DISABLE;
7306937602eSMichael Walle return 0;
7316937602eSMichael Walle }
7326937602eSMichael Walle
7336937602eSMichael Walle val = bcm_phy_read_rdb(phydev, BCM54140_RDB_SPARE2);
7346937602eSMichael Walle if (val < 0)
7356937602eSMichael Walle return val;
7366937602eSMichael Walle
7376937602eSMichael Walle if (val & BCM54140_RDB_SPARE2_WS_RTRY_DIS)
7386937602eSMichael Walle *data = 1;
7396937602eSMichael Walle else
7406937602eSMichael Walle *data = FIELD_GET(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, val) + 2;
7416937602eSMichael Walle
7426937602eSMichael Walle return 0;
7436937602eSMichael Walle }
7446937602eSMichael Walle
bcm54140_set_downshift(struct phy_device * phydev,u8 cnt)7456937602eSMichael Walle static int bcm54140_set_downshift(struct phy_device *phydev, u8 cnt)
7466937602eSMichael Walle {
7476937602eSMichael Walle u16 mask, set;
7486937602eSMichael Walle int ret;
7496937602eSMichael Walle
7506937602eSMichael Walle if (cnt > BCM54140_MAX_DOWNSHIFT && cnt != DOWNSHIFT_DEV_DEFAULT_COUNT)
7516937602eSMichael Walle return -EINVAL;
7526937602eSMichael Walle
7536937602eSMichael Walle if (!cnt)
7546937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
7556937602eSMichael Walle BCM54140_RDB_C_MISC_CTRL_WS_EN, 0);
7566937602eSMichael Walle
7576937602eSMichael Walle if (cnt == DOWNSHIFT_DEV_DEFAULT_COUNT)
7586937602eSMichael Walle cnt = BCM54140_DEFAULT_DOWNSHIFT;
7596937602eSMichael Walle
7606937602eSMichael Walle if (cnt == 1) {
7616937602eSMichael Walle mask = 0;
7626937602eSMichael Walle set = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
7636937602eSMichael Walle } else {
7646937602eSMichael Walle mask = BCM54140_RDB_SPARE2_WS_RTRY_DIS;
7656937602eSMichael Walle mask |= BCM54140_RDB_SPARE2_WS_RTRY_LIMIT;
7666937602eSMichael Walle set = FIELD_PREP(BCM54140_RDB_SPARE2_WS_RTRY_LIMIT, cnt - 2);
7676937602eSMichael Walle }
7686937602eSMichael Walle ret = bcm_phy_modify_rdb(phydev, BCM54140_RDB_SPARE2,
7696937602eSMichael Walle mask, set);
7706937602eSMichael Walle if (ret)
7716937602eSMichael Walle return ret;
7726937602eSMichael Walle
7736937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_MISC_CTRL,
7746937602eSMichael Walle 0, BCM54140_RDB_C_MISC_CTRL_WS_EN);
7756937602eSMichael Walle }
7766937602eSMichael Walle
bcm54140_get_edpd(struct phy_device * phydev,u16 * tx_interval)7776937602eSMichael Walle static int bcm54140_get_edpd(struct phy_device *phydev, u16 *tx_interval)
7786937602eSMichael Walle {
7796937602eSMichael Walle int val;
7806937602eSMichael Walle
7816937602eSMichael Walle val = bcm_phy_read_rdb(phydev, BCM54140_RDB_C_APWR);
7826937602eSMichael Walle if (val < 0)
7836937602eSMichael Walle return val;
7846937602eSMichael Walle
7856937602eSMichael Walle switch (FIELD_GET(BCM54140_RDB_C_APWR_APD_MODE_MASK, val)) {
7866937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_DIS:
7876937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_DIS2:
7886937602eSMichael Walle *tx_interval = ETHTOOL_PHY_EDPD_DISABLE;
7896937602eSMichael Walle break;
7906937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_EN:
7916937602eSMichael Walle case BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG:
7926937602eSMichael Walle switch (FIELD_GET(BCM54140_RDB_C_APWR_SLP_TIM_MASK, val)) {
7936937602eSMichael Walle case BCM54140_RDB_C_APWR_SLP_TIM_2_7:
7946937602eSMichael Walle *tx_interval = 2700;
7956937602eSMichael Walle break;
7966937602eSMichael Walle case BCM54140_RDB_C_APWR_SLP_TIM_5_4:
7976937602eSMichael Walle *tx_interval = 5400;
7986937602eSMichael Walle break;
7996937602eSMichael Walle }
8006937602eSMichael Walle }
8016937602eSMichael Walle
8026937602eSMichael Walle return 0;
8036937602eSMichael Walle }
8046937602eSMichael Walle
bcm54140_set_edpd(struct phy_device * phydev,u16 tx_interval)8056937602eSMichael Walle static int bcm54140_set_edpd(struct phy_device *phydev, u16 tx_interval)
8066937602eSMichael Walle {
8076937602eSMichael Walle u16 mask, set;
8086937602eSMichael Walle
8096937602eSMichael Walle mask = BCM54140_RDB_C_APWR_APD_MODE_MASK;
8106937602eSMichael Walle if (tx_interval == ETHTOOL_PHY_EDPD_DISABLE)
8116937602eSMichael Walle set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
8126937602eSMichael Walle BCM54140_RDB_C_APWR_APD_MODE_DIS);
8136937602eSMichael Walle else
8146937602eSMichael Walle set = FIELD_PREP(BCM54140_RDB_C_APWR_APD_MODE_MASK,
8156937602eSMichael Walle BCM54140_RDB_C_APWR_APD_MODE_EN_ANEG);
8166937602eSMichael Walle
8176937602eSMichael Walle /* enable single pulse mode */
8186937602eSMichael Walle set |= BCM54140_RDB_C_APWR_SINGLE_PULSE;
8196937602eSMichael Walle
8206937602eSMichael Walle /* set sleep timer */
8216937602eSMichael Walle mask |= BCM54140_RDB_C_APWR_SLP_TIM_MASK;
8226937602eSMichael Walle switch (tx_interval) {
8236937602eSMichael Walle case ETHTOOL_PHY_EDPD_DFLT_TX_MSECS:
8246937602eSMichael Walle case ETHTOOL_PHY_EDPD_DISABLE:
8256937602eSMichael Walle case 2700:
8266937602eSMichael Walle set |= BCM54140_RDB_C_APWR_SLP_TIM_2_7;
8276937602eSMichael Walle break;
8286937602eSMichael Walle case 5400:
8296937602eSMichael Walle set |= BCM54140_RDB_C_APWR_SLP_TIM_5_4;
8306937602eSMichael Walle break;
8316937602eSMichael Walle default:
8326937602eSMichael Walle return -EINVAL;
8336937602eSMichael Walle }
8346937602eSMichael Walle
8356937602eSMichael Walle return bcm_phy_modify_rdb(phydev, BCM54140_RDB_C_APWR, mask, set);
8366937602eSMichael Walle }
8376937602eSMichael Walle
bcm54140_get_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,void * data)8386937602eSMichael Walle static int bcm54140_get_tunable(struct phy_device *phydev,
8396937602eSMichael Walle struct ethtool_tunable *tuna, void *data)
8406937602eSMichael Walle {
8416937602eSMichael Walle switch (tuna->id) {
8426937602eSMichael Walle case ETHTOOL_PHY_DOWNSHIFT:
8436937602eSMichael Walle return bcm54140_get_downshift(phydev, data);
8446937602eSMichael Walle case ETHTOOL_PHY_EDPD:
8456937602eSMichael Walle return bcm54140_get_edpd(phydev, data);
8466937602eSMichael Walle default:
8476937602eSMichael Walle return -EOPNOTSUPP;
8486937602eSMichael Walle }
8496937602eSMichael Walle }
8506937602eSMichael Walle
bcm54140_set_tunable(struct phy_device * phydev,struct ethtool_tunable * tuna,const void * data)8516937602eSMichael Walle static int bcm54140_set_tunable(struct phy_device *phydev,
8526937602eSMichael Walle struct ethtool_tunable *tuna, const void *data)
8536937602eSMichael Walle {
8546937602eSMichael Walle switch (tuna->id) {
8556937602eSMichael Walle case ETHTOOL_PHY_DOWNSHIFT:
8566937602eSMichael Walle return bcm54140_set_downshift(phydev, *(const u8 *)data);
8576937602eSMichael Walle case ETHTOOL_PHY_EDPD:
8586937602eSMichael Walle return bcm54140_set_edpd(phydev, *(const u16 *)data);
8596937602eSMichael Walle default:
8606937602eSMichael Walle return -EOPNOTSUPP;
8616937602eSMichael Walle }
8626937602eSMichael Walle }
8636937602eSMichael Walle
8646937602eSMichael Walle static struct phy_driver bcm54140_drivers[] = {
8656937602eSMichael Walle {
8666937602eSMichael Walle .phy_id = PHY_ID_BCM54140,
867e4e51da6SMichael Walle .phy_id_mask = BCM54140_PHY_ID_MASK,
8686937602eSMichael Walle .name = "Broadcom BCM54140",
869f956af3fSMichael Walle .flags = PHY_POLL_CABLE_TEST,
8706937602eSMichael Walle .features = PHY_GBIT_FEATURES,
8716937602eSMichael Walle .config_init = bcm54140_config_init,
8724567d5c3SIoana Ciornei .handle_interrupt = bcm54140_handle_interrupt,
8736937602eSMichael Walle .config_intr = bcm54140_config_intr,
8746937602eSMichael Walle .probe = bcm54140_probe,
8756937602eSMichael Walle .suspend = genphy_suspend,
8766937602eSMichael Walle .resume = genphy_resume,
87786570d8aSMichael Walle .soft_reset = genphy_soft_reset,
8786937602eSMichael Walle .get_tunable = bcm54140_get_tunable,
8796937602eSMichael Walle .set_tunable = bcm54140_set_tunable,
880f956af3fSMichael Walle .cable_test_start = bcm_phy_cable_test_start_rdb,
881f956af3fSMichael Walle .cable_test_get_status = bcm_phy_cable_test_get_status_rdb,
8826937602eSMichael Walle },
8836937602eSMichael Walle };
8846937602eSMichael Walle module_phy_driver(bcm54140_drivers);
8856937602eSMichael Walle
8866937602eSMichael Walle static struct mdio_device_id __maybe_unused bcm54140_tbl[] = {
887e4e51da6SMichael Walle { PHY_ID_BCM54140, BCM54140_PHY_ID_MASK },
8886937602eSMichael Walle { }
8896937602eSMichael Walle };
8906937602eSMichael Walle
8916937602eSMichael Walle MODULE_AUTHOR("Michael Walle");
8926937602eSMichael Walle MODULE_DESCRIPTION("Broadcom BCM54140 PHY driver");
8936937602eSMichael Walle MODULE_DEVICE_TABLE(mdio, bcm54140_tbl);
8946937602eSMichael Walle MODULE_LICENSE("GPL");
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