1 // SPDX-License-Identifier: GPL-2.0
10 #include <dt-bindings/phy/phy.h>
21 #include "phy-mtk-io.h"
86 /* PHY switch between pcie/usb3/sgmii */
124 	void __iomem *pbase = inst->port_base;  in u2_phy_slew_rate_calibrate()
130 	if (inst->eye_src)  in u2_phy_slew_rate_calibrate()
160 		/* (1024 / FM_OUT) x reference clock frequency x coefficient */  in u2_phy_slew_rate_calibrate()
161 		tmp = xsphy->src_ref_clk * xsphy->src_coef;  in u2_phy_slew_rate_calibrate()
168 	dev_dbg(xsphy->dev, "phy.%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",  in u2_phy_slew_rate_calibrate()
169 		inst->index, fm_out, calib_val,  in u2_phy_slew_rate_calibrate()
170 		xsphy->src_ref_clk, xsphy->src_coef);  in u2_phy_slew_rate_calibrate()
182 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_init()
193 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_power_on()
194 	u32 index = inst->index;  in u2_phy_instance_power_on()
202 	dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_on()
208 	void __iomem *pbase = inst->port_base;  in u2_phy_instance_power_off()
209 	u32 index = inst->index;  in u2_phy_instance_power_off()
217 	dev_dbg(xsphy->dev, "%s(%d)\n", __func__, index);  in u2_phy_instance_power_off()
226 	tmp = readl(inst->port_base + XSP_U2PHYDTM1);  in u2_phy_instance_set_mode()
227 	switch (mode) {  in u2_phy_instance_set_mode()
241 	writel(tmp, inst->port_base + XSP_U2PHYDTM1);  in u2_phy_instance_set_mode()
247 	struct device *dev = &inst->phy->dev;  in phy_parse_property()
249 	switch (inst->type) {  in phy_parse_property()
251 		device_property_read_u32(dev, "mediatek,efuse-intr",  in phy_parse_property()
252 					 &inst->efuse_intr);  in phy_parse_property()
253 		device_property_read_u32(dev, "mediatek,eye-src",  in phy_parse_property()
254 					 &inst->eye_src);  in phy_parse_property()
255 		device_property_read_u32(dev, "mediatek,eye-vrt",  in phy_parse_property()
256 					 &inst->eye_vrt);  in phy_parse_property()
257 		device_property_read_u32(dev, "mediatek,eye-term",  in phy_parse_property()
258 					 &inst->eye_term);  in phy_parse_property()
260 			inst->efuse_intr, inst->eye_src,  in phy_parse_property()
261 			inst->eye_vrt, inst->eye_term);  in phy_parse_property()
264 		device_property_read_u32(dev, "mediatek,efuse-intr",  in phy_parse_property()
265 					 &inst->efuse_intr);  in phy_parse_property()
266 		device_property_read_u32(dev, "mediatek,efuse-tx-imp",  in phy_parse_property()
267 					 &inst->efuse_tx_imp);  in phy_parse_property()
268 		device_property_read_u32(dev, "mediatek,efuse-rx-imp",  in phy_parse_property()
269 					 &inst->efuse_rx_imp);  in phy_parse_property()
270 		dev_dbg(dev, "intr:%d, tx-imp:%d, rx-imp:%d\n",  in phy_parse_property()
271 			inst->efuse_intr, inst->efuse_tx_imp,  in phy_parse_property()
272 			inst->efuse_rx_imp);  in phy_parse_property()
279 		dev_err(xsphy->dev, "incompatible phy type\n");  in phy_parse_property()
287 	void __iomem *pbase = inst->port_base;  in u2_phy_props_set()
289 	if (inst->efuse_intr)  in u2_phy_props_set()
291 				     inst->efuse_intr);  in u2_phy_props_set()
293 	if (inst->eye_src)  in u2_phy_props_set()
295 				     inst->eye_src);  in u2_phy_props_set()
297 	if (inst->eye_vrt)  in u2_phy_props_set()
299 				     inst->eye_vrt);  in u2_phy_props_set()
301 	if (inst->eye_term)  in u2_phy_props_set()
303 				     inst->eye_term);  in u2_phy_props_set()
309 	void __iomem *pbase = inst->port_base;  in u3_phy_props_set()
311 	if (inst->efuse_intr)  in u3_phy_props_set()
312 		mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00,  in u3_phy_props_set()
313 				     RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr);  in u3_phy_props_set()
315 	if (inst->efuse_tx_imp)  in u3_phy_props_set()
317 				     RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp);  in u3_phy_props_set()
319 	if (inst->efuse_rx_imp)  in u3_phy_props_set()
321 				     RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);  in u3_phy_props_set()
324 /* type switch for usb3/pcie/sgmii */
331 	/* type switch function is optional */  in phy_type_syscon_get()
332 	if (!of_property_present(dn, "mediatek,syscon-type"))  in phy_type_syscon_get()
335 	ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type",  in phy_type_syscon_get()
340 	instance->type_sw_reg = args.args[0];  in phy_type_syscon_get()
341 	instance->type_sw_index = args.args[1] & 0x3; /* <=3 */  in phy_type_syscon_get()
342 	instance->type_sw = syscon_node_to_regmap(args.np);  in phy_type_syscon_get()
344 	dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n",  in phy_type_syscon_get()
345 		 instance->type_sw_reg, instance->type_sw_index);  in phy_type_syscon_get()
347 	return PTR_ERR_OR_ZERO(instance->type_sw);  in phy_type_syscon_get()
355 	if (!instance->type_sw)  in phy_type_set()
358 	switch (instance->type) {  in phy_type_set()
373 	offset = instance->type_sw_index * BITS_PER_BYTE;  in phy_type_set()
374 	regmap_update_bits(instance->type_sw, instance->type_sw_reg,  in phy_type_set()
383 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_init()
386 	ret = clk_prepare_enable(inst->ref_clk);  in mtk_phy_init()
388 		dev_err(xsphy->dev, "failed to enable ref_clk\n");  in mtk_phy_init()
392 	switch (inst->type) {  in mtk_phy_init()
405 		dev_err(xsphy->dev, "incompatible phy type\n");  in mtk_phy_init()
406 		clk_disable_unprepare(inst->ref_clk);  in mtk_phy_init()
407 		return -EINVAL;  in mtk_phy_init()
416 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_on()
418 	if (inst->type == PHY_TYPE_USB2) {  in mtk_phy_power_on()
429 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_power_off()
431 	if (inst->type == PHY_TYPE_USB2)  in mtk_phy_power_off()
441 	clk_disable_unprepare(inst->ref_clk);  in mtk_phy_exit()
448 	struct mtk_xsphy *xsphy = dev_get_drvdata(phy->dev.parent);  in mtk_phy_set_mode()
450 	if (inst->type == PHY_TYPE_USB2)  in mtk_phy_set_mode()
461 	struct device_node *phy_np = args->np;  in mtk_phy_xlate()
464 	if (args->args_count != 1) {  in mtk_phy_xlate()
466 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
469 	for (index = 0; index < xsphy->nphys; index++)  in mtk_phy_xlate()
470 		if (phy_np == xsphy->phys[index]->phy->dev.of_node) {  in mtk_phy_xlate()
471 			inst = xsphy->phys[index];  in mtk_phy_xlate()
477 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
480 	inst->type = args->args[0];  in mtk_phy_xlate()
481 	if (!(inst->type == PHY_TYPE_USB2 ||  in mtk_phy_xlate()
482 	      inst->type == PHY_TYPE_USB3 ||  in mtk_phy_xlate()
483 	      inst->type == PHY_TYPE_PCIE ||  in mtk_phy_xlate()
484 	      inst->type == PHY_TYPE_SGMII)) {  in mtk_phy_xlate()
485 		dev_err(dev, "unsupported phy type: %d\n", inst->type);  in mtk_phy_xlate()
486 		return ERR_PTR(-EINVAL);  in mtk_phy_xlate()
492 	return inst->phy;  in mtk_phy_xlate()
512 	struct device *dev = &pdev->dev;  in mtk_xsphy_probe()
513 	struct device_node *np = dev->of_node;  in mtk_xsphy_probe()
522 		return -ENOMEM;  in mtk_xsphy_probe()
524 	xsphy->nphys = of_get_child_count(np);  in mtk_xsphy_probe()
525 	xsphy->phys = devm_kcalloc(dev, xsphy->nphys,  in mtk_xsphy_probe()
526 				       sizeof(*xsphy->phys), GFP_KERNEL);  in mtk_xsphy_probe()
527 	if (!xsphy->phys)  in mtk_xsphy_probe()
528 		return -ENOMEM;  in mtk_xsphy_probe()
530 	xsphy->dev = dev;  in mtk_xsphy_probe()
537 		xsphy->glb_base = devm_ioremap_resource(dev, glb_res);  in mtk_xsphy_probe()
538 		if (IS_ERR(xsphy->glb_base)) {  in mtk_xsphy_probe()
540 			return PTR_ERR(xsphy->glb_base);  in mtk_xsphy_probe()
544 	xsphy->src_ref_clk = XSP_REF_CLK;  in mtk_xsphy_probe()
545 	xsphy->src_coef = XSP_SLEW_RATE_COEF;  in mtk_xsphy_probe()
547 	device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",  in mtk_xsphy_probe()
548 				 &xsphy->src_ref_clk);  in mtk_xsphy_probe()
549 	device_property_read_u32(dev, "mediatek,src-coef", &xsphy->src_coef);  in mtk_xsphy_probe()
559 			return -ENOMEM;  in mtk_xsphy_probe()
561 		xsphy->phys[port] = inst;  in mtk_xsphy_probe()
571 			dev_err(dev, "failed to get address resource(id-%d)\n",  in mtk_xsphy_probe()
576 		inst->port_base = devm_ioremap_resource(&phy->dev, &res);  in mtk_xsphy_probe()
577 		if (IS_ERR(inst->port_base)) {  in mtk_xsphy_probe()
579 			return PTR_ERR(inst->port_base);  in mtk_xsphy_probe()
582 		inst->phy = phy;  in mtk_xsphy_probe()
583 		inst->index = port;  in mtk_xsphy_probe()
587 		inst->ref_clk = devm_clk_get(&phy->dev, "ref");  in mtk_xsphy_probe()
588 		if (IS_ERR(inst->ref_clk)) {  in mtk_xsphy_probe()
589 			dev_err(dev, "failed to get ref_clk(id-%d)\n", port);  in mtk_xsphy_probe()
590 			return PTR_ERR(inst->ref_clk);  in mtk_xsphy_probe()
605 		.name	= "mtk-xsphy",
613 MODULE_DESCRIPTION("MediaTek USB XS-PHY driver");