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/freebsd/sys/contrib/device-tree/Bindings/reset/
H A Dnuvoton,npcm-reset.txt1 Nuvoton NPCM Reset controller
4 - compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
5 - reg : specifies physical base address and size of the register.
6 - #reset-cells: must be set to 2
9 - nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
10 NPCM7xx contain four software reset that represent numbers 1 to 4.
12 If 'nuvoton,sw-reset-number' is not specified software reset is disabled.
16 compatible = "nuvoton,npcm750-reset";
18 #reset-cells = <2>;
19 nuvoton,sw-reset-number = <2>;
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H A Dnuvoton,npcm750-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,npcm750-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Reset controller
10 - Tomer Maimon <tmaimon77@gmail.com>
15 - nuvoton,npcm750-reset # Poleg NPCM7XX SoC
16 - nuvoton,npcm845-reset # Arbel NPCM8XX SoC
21 '#reset-cells':
28 nuvoton,sw-reset-number:
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/freebsd/sys/dev/e1000/
H A De1000_api.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 * e1000_init_mac_params - Initialize MAC function pointers
48 if (hw->mac.ops.init_params) { in e1000_init_mac_params()
49 ret_val = hw->mac.ops.init_params(hw); in e1000_init_mac_params()
56 ret_val = -E1000_ERR_CONFIG; in e1000_init_mac_params()
64 * e1000_init_nvm_params - Initialize NVM function pointers
74 if (hw->nvm.ops.init_params) { in e1000_init_nvm_params()
75 ret_val = hw->nvm.ops.init_params(hw); in e1000_init_nvm_params()
82 ret_val = -E1000_ERR_CONFIG; in e1000_init_nvm_params()
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H A De1000_82543.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
86 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82543()
91 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82543()
92 phy->type = e1000_phy_none; in e1000_init_phy_params_82543()
95 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82543()
96 phy->ops.power_down = e1000_power_down_phy_copper; in e1000_init_phy_params_82543()
99 phy->addr = 1; in e1000_init_phy_params_82543()
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82543()
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H A De1000_defines.h2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
69 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
70 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
71 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
78 /* Physical Func Reset Done Indication */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
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H A De1000_mac.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
42 * e1000_init_mac_ops_generic - Initialize MAC function pointers
45 * Setups up the function pointers to no-op functions
49 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_ops_generic()
53 mac->ops.init_params = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
54 mac->ops.init_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
55 mac->ops.reset_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
56 mac->ops.setup_physical_interface = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
57 mac->ops.get_bus_info = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
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/freebsd/sys/dev/ixgbe/
H A Dixgbe_x540.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type
61 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_X540()
62 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_init_ops_X540()
63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_X540()
74 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; in ixgbe_init_ops_X540()
75 eeprom->ops.read = ixgbe_read_eerd_X540; in ixgbe_init_ops_X540()
76 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; in ixgbe_init_ops_X540()
77 eeprom->ops.write = ixgbe_write_eewr_X540; in ixgbe_init_ops_X540()
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/freebsd/sys/dev/ichiic/
H A Dig4_reg.h40 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf
42 * This is a from-scratch driver under the BSD license using the Intel data
61 * Register width is 32-bits
63 * 22.2 Default Values on device reset ar
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/freebsd/contrib/ofed/opensm/opensm/
H A Dosm_ucast_dfsssp.c2 * Copyright (c) 2004-2008 Voltaire, Inc. All rights reserved.
3 * Copyright (c) 2002-2015 Mellanox Technologies LTD. All rights reserved.
4 * Copyright (c) 1996-2003 Intel Corporation. All rights reserved.
5 * Copyright (c) 2009-2015 ZIH, TU Dresden, Federal Republic of Germany. All rights reserved.
6 * Copyright (C) 2012-2017 Tokyo Institute of Technology. All rights reserved.
18 * - Redistributions of source code must retain the above
22 * - Redistributions in binary form must reproduce the above
40 * Implementation of OpenSM (deadlock-free) single-source-shortest-path routing
97 osm_switch_t *sw; /* selfpointer */ member
109 uint8_t *vls; /* matrix form assignment lid X lid -> virtual lane */
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/freebsd/sys/contrib/device-tree/Bindings/thermal/
H A Dnvidia,tegra124-soctherm.txt4 or interrupt-based thermal monitoring, CPU and GPU throttling based
10 - compatible : For Tegra124, must contain "nvidia,tegra124-soctherm".
11 For Tegra132, must contain "nvidia,tegra132-soctherm".
12 For Tegra210, must contain "nvidia,tegra210-soctherm".
13 - reg : Should contain at least 2 entries for each entry in reg-names:
14 - SOCTHERM register set
15 - Tegra CAR register set: Required for Tegra124 and Tegra210.
16 - CCROC register set: Required for Tegra132.
17 - reg-names : Should contain at least 2 entries:
18 - soctherm-reg
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H A Dnvidia,tegra124-soctherm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/thermal/nvidia,tegra124-soctherm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 polled or interrupt-based thermal monitoring, CPU and GPU throttling based
21 - nvidia,tegra124-soctherm
22 - nvidia,tegra132-soctherm
23 - nvidia,tegra210-soctherm
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/freebsd/contrib/opencsd/decoder/include/opencsd/
H A Dtrc_gen_elem_types.h39 * @brief Generic trace elements output by the PE trace decode and SW stim decode stages.
49 …OCSD_GEN_TRC_ELEM_UNKNOWN = 0, /*!< Unknown trace element - default value or indicate error in…
50 …OCSD_GEN_TRC_ELEM_NO_SYNC, /*!< Waiting for sync - either at start of decode, or after ove…
51 …OCSD_GEN_TRC_ELEM_TRACE_ON, /*!< Start of trace - beginning of elements or restart after di…
57 … OCSD_GEN_TRC_ELEM_ADDR_UNKNOWN, /*!< address currently unknown - need address packet update */
58 …OCSD_GEN_TRC_ELEM_EXCEPTION, /*!< exception - start address may be exception target, end add…
60 …OCSD_GEN_TRC_ELEM_TIMESTAMP, /*!< Timestamp - preceding elements happeded before this time. …
61 …OCSD_GEN_TRC_ELEM_CYCLE_COUNT, /*!< Cycle count - cycles since last cycle count value - associ…
62 OCSD_GEN_TRC_ELEM_EVENT, /*!< Event - trigger or numbered event */
63 …OCSD_GEN_TRC_ELEM_SWTRACE, /*!< Software trace packet - may contain data payload. STM / IT…
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/freebsd/sys/dev/igc/
H A Digc_i225.c1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
22 * igc_init_nvm_params_i225 - Init NVM func ptrs.
27 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_i225()
36 * Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_i225()
47 nvm->word_size = 1 << size; in igc_init_nvm_params_i225()
48 nvm->opcode_bits = 8; in igc_init_nvm_params_i225()
49 nvm->delay_usec = 1; in igc_init_nvm_params_i225()
50 nvm->type = igc_nvm_eeprom_spi; in igc_init_nvm_params_i225()
53 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; in igc_init_nvm_params_i225()
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H A Digc_api.c1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
11 * igc_init_mac_params - Initialize MAC function pointers
21 if (hw->mac.ops.init_params) { in igc_init_mac_params()
22 ret_val = hw->mac.ops.init_params(hw); in igc_init_mac_params()
29 ret_val = -IGC_ERR_CONFIG; in igc_init_mac_params()
37 * igc_init_nvm_params - Initialize NVM function pointers
47 if (hw->nvm.ops.init_params) { in igc_init_nvm_params()
48 ret_val = hw->nvm.ops.init_params(hw); in igc_init_nvm_params()
55 ret_val = -IGC_ERR_CONFIG; in igc_init_nvm_params()
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H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
59 #define IGC_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
60 #define IGC_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
61 #define IGC_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
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/freebsd/sys/dev/ice/
H A Dice_common.c1 /* SPDX-License-Identifier: BSD-3-Clause */
127 * ice_dump_phy_type - helper function to dump phy_type
158 * ice_set_mac_type - Sets MAC type
168 if (hw->vendor_id != ICE_INTEL_VENDOR_ID) in ice_set_mac_type()
171 switch (hw->device_id) { in ice_set_mac_type()
178 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
199 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
205 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
225 hw->mac_type = ICE_MAC_E830; in ice_set_mac_type()
228 hw->mac_type = ICE_MAC_UNKNOWN; in ice_set_mac_type()
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H A Dice_switch.c1 /* SPDX-License-Identifier: BSD-3-Clause */
68 * ice_init_def_sw_recp - initialize the recipe book keeping tables
70 * @recp_list: pointer to sw recipe list
100 * ice_aq_get_sw_cfg - get switch configuration
105 * @num_elems: pointer to number of elements
109 * This admin command returns information such as initial VSI/port number
115 * configuration information has been returned; if non-zer
1548 struct ice_switch_info *sw = hw->switch_info; ice_create_vsi_list_map() local
1765 struct ice_switch_info *sw = NULL; ice_update_sw_rule_bridge_mode() local
2339 ice_add_mac_rule(struct ice_hw * hw,struct LIST_HEAD_TYPE * m_list,struct ice_switch_info * sw,u8 lport) ice_add_mac_rule() argument
2659 ice_add_vlan_rule(struct ice_hw * hw,struct LIST_HEAD_TYPE * v_list,struct ice_switch_info * sw) ice_add_vlan_rule() argument
2706 ice_add_eth_mac_rule(struct ice_hw * hw,struct LIST_HEAD_TYPE * em_list,struct ice_switch_info * sw,u8 lport) ice_add_eth_mac_rule() argument
2756 ice_remove_eth_mac_rule(struct ice_hw * hw,struct LIST_HEAD_TYPE * em_list,struct ice_switch_info * sw) ice_remove_eth_mac_rule() argument
2898 struct ice_switch_info *sw = hw->switch_info; ice_rem_all_sw_rules_info() local
3298 _ice_get_vsi_promisc(struct ice_hw * hw,u16 vsi_handle,ice_bitmap_t * promisc_mask,u16 * vid,struct ice_switch_info * sw,enum ice_sw_lkup_type lkup) _ice_get_vsi_promisc() argument
3406 _ice_clear_vsi_promisc(struct ice_hw * hw,u16 vsi_handle,ice_bitmap_t * promisc_mask,u16 vid,struct ice_switch_info * sw) _ice_clear_vsi_promisc() argument
3506 _ice_set_vsi_promisc(struct ice_hw * hw,u16 vsi_handle,ice_bitmap_t * promisc_mask,u16 vid,u8 lport,struct ice_switch_info * sw) _ice_set_vsi_promisc() argument
3653 _ice_set_vlan_vsi_promisc(struct ice_hw * hw,u16 vsi_handle,ice_bitmap_t * promisc_mask,bool rm_vlan_promisc,u8 lport,struct ice_switch_info * sw) _ice_set_vlan_vsi_promisc() argument
3795 ice_remove_vsi_fltr_rule(struct ice_hw * hw,u16 vsi_handle,struct ice_switch_info * sw) ice_remove_vsi_fltr_rule() argument
4199 struct ice_switch_info *sw = hw->switch_info; ice_replay_all_fltr() local
4227 ice_replay_vsi_fltr(struct ice_hw * hw,struct ice_port_info * pi,struct ice_switch_info * sw,u16 vsi_handle,u8 recp_id,struct LIST_HEAD_TYPE * list_head) ice_replay_vsi_fltr() argument
4292 struct ice_switch_info *sw = NULL; ice_replay_vsi_all_fltr() local
4320 ice_rm_sw_replay_rule_info(struct ice_hw * hw,struct ice_switch_info * sw) ice_rm_sw_replay_rule_info() argument
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H A Dice_sched.c1 /* SPDX-License-Identifier: BSD-3-Clause */
35 * ice_sched_add_root_node - Insert the Tx scheduler root node in SW DB
40 * to the SW DB.
52 hw = pi->hw; in ice_sched_add_root_node()
58 root->children = (struct ice_sched_node **) in ice_sched_add_root_node()
59 ice_calloc(hw, hw->max_childre in ice_sched_add_root_node()
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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Dsnps,dwc-qos-ethernet.txt7 IP block. The IP supports multiple options for bus type, clocking and reset
8 structure, and feature list. Consequently, a number of properties and list
13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidi
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H A Dmicrochip,sparx5-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The SparX-5 Enterprise Ethernet switch family provides a rich set of
15 Enterprise switching features such as advanced TCAM-based VLAN and
17 security through TCAM-based frame processing using versatile content
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212_beacon.c1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
52 * + Timer 0 - 0..15 0xffff TU in ar5212SetBeaconTimers()
53 * + Timer 1 - 0..18 0x7ffff TU/8 in ar5212SetBeaconTimers()
54 * + Timer 2 - 0..24 0x1ffffff TU/8 in ar5212SetBeaconTimers()
55 * + Timer 3 - 0..15 0xffff TU in ar5212SetBeaconTimers()
57 OS_REG_WRITE(ah, AR_TIMER0, bt->bt_nexttbtt & 0xffff); in ar5212SetBeaconTimers()
58 OS_REG_WRITE(ah, AR_TIMER1, bt->bt_nextdba & 0x7ffff); in ar5212SetBeaconTimers()
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/freebsd/sys/contrib/device-tree/Bindings/pci/
H A Dnvidia,tegra194-pcie.txt4 and thus inherits all the common properties defined in snps,dw-pcie.yaml and
5 snps,dw-pcie-ep.yaml.
10 - power-domains: A phandle to the node that controls power to the respective
20 "include/dt-bindings/power/tegra194-powergate.h" file.
21 - reg: A list of physical base address and length pairs for each set of
22 controller registers. Must contain an entry for each entry in the reg-names
24 - reg-names: Must include the following entries:
26 "config": As per the definition in snps,dw-pcie.yaml
29 for SW access.
32 - interrupts: A list of interrupt outputs of the controller. Must contain an
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/freebsd/sys/dev/netmap/
H A Dnetmap_bdg.c2 * Copyright (C) 2013-2016 Universita` di Pisa
31 --- VALE SWITCH ---
44 On the rx ring, the per-port lock is grabbed initially to reserve
45 a number of slot in the ring, then the lock is released,
54 * OS-specific code that is used only within this file.
55 * Other OS-specific code that must be accessed by drivers
114 struct nm_bridge *b = vp->na_bdg; in netmap_bdg_name()
117 return b->bdg_basename; in netmap_bdg_name()
145 int colon_pos = -1; in nm_bdg_name_validate()
149 return -1; in nm_bdg_name_validate()
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/freebsd/sys/dev/atkbdc/
H A Datkbd.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 1999 Kazutaka YOKOTA <yokota@zodiac.mech.utsunomiya-u.ac.jp>
85 #define HAS_QUIRK(p, q) (((atkbdc_softc_t *)(p))->quirks & q)
99 keyboard_switch_t *sw; in atkbd_probe_unit() local
103 sw = kbd_get_switch(ATKBD_DRIVER_NAME); in atkbd_probe_unit()
104 if (sw == NULL) in atkbd_probe_unit()
109 error = (*sw->probe)(device_get_unit(dev), args, flags); in atkbd_probe_unit()
118 keyboard_switch_t *sw; in atkbd_attach_unit() local
124 sw = kbd_get_switch(ATKBD_DRIVER_NAME); in atkbd_attach_unit()
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/freebsd/contrib/nvi/ex/
H A Dex_txt.c1 /*-
47 * ex_txt --
68 * to 0 -- text_init() handles this.) in ex_txt()
72 if (TAILQ_NEXT(tp, q) != NULL || tp->lb_len < 32) { in ex_txt()
76 tp->len = 0; in ex_txt()
83 /* Set the starting line number. */ in ex_txt()
84 tp->lno = sp->lno + 1; in ex_txt()
98 gp = sp->gp; in ex_txt()
104 if (v_txt_auto(sp, sp->lno, NULL, 0, tp)) in ex_txt()
114 /* Deal with all non-character events. */ in ex_txt()
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