Lines Matching +full:sw +full:- +full:reset +full:- +full:number
2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
69 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
70 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
71 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
78 /* Physical Func Reset Done Indication */
94 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
122 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
172 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
173 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
188 #define E1000_RCTL_RST 0x00000001 /* Software reset */
260 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
261 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
263 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
270 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */
271 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */
282 #define E1000_CTRL_DEV_RST 0x20000000 /* Device reset */
283 #define E1000_CTRL_RST 0x04000000 /* Global reset */
287 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
334 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
340 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
341 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
343 /* Constants used to interpret the masked PCI-X bus speed. */
344 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus spd 50-66MHz */
345 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus spd 66-100MHz */
346 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus spd 100-133MHz*/
365 /* 1000/H is not supported, nor spec-compliant. */
420 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
535 /* SW Semaphore Register */
560 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
628 #define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */
670 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
693 * Number of high/low register pairs in the RAR. The RAR (Receive Address
727 /* Loop limit on how long we wait for auto-negotiation to complete */
732 /* Number of 100 microseconds we wait for PCI Express master disable */
734 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
736 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
738 /* Number of milliseconds for NVM auto read done after MAC reset. */
751 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
932 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
986 /* 1000BASE-T Control Register */
1002 /* 1000BASE-T Status Register */
1025 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
1026 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
1046 #define E1000_EECD_TYPE 0x00002000 /* NVM Type (1-SPI, 0-Microwire) */
1174 /* length of string needed to store PBA number */
1180 /* PBA (printed board assembly) number words */
1192 /* NVM Commands - Microwire */
1199 /* NVM Commands - SPI */
1203 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1231 /* PCI/PCI-X/PCI-EX Config space */
1255 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1296 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1306 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1317 * 1 = 50-80M
1318 * 2 = 80-110M
1319 * 3 = 110-140M
1332 /* Number of times we will attempt to autonegotiate before downshifting if we
1337 /* Number of times we will attempt to autonegotiate before downshifting if we
1351 /* Number of times we will attempt to autonegotiate before downshifting if we
1382 * 15-5: page
1383 * 4-0: register offset
1401 /* Page 193 - Port Control Registers */
1406 /* Page 194 - KMRN Registers */
1450 /* Tx Rate-Scheduler Config fields */
1467 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1512 #define E1000_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1514 #define E1000_VTCTRL_RST 0x04000000 /* Reset VF */