Lines Matching +full:sw +full:- +full:reset +full:- +full:number
1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
59 #define IGC_CTRL_EXT_SDP4_DATA 0x00000010 /* SW Definable Pin 4 data */
60 #define IGC_CTRL_EXT_SDP6_DATA 0x00000040 /* SW Definable Pin 6 data */
61 #define IGC_CTRL_EXT_SDP3_DATA 0x00000080 /* SW Definable Pin 3 data */
72 #define IGC_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
89 #define IGC_RXD_STAT_PIF 0x80 /* passed in-exact filter */
127 #define IGC_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
128 #define IGC_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
143 #define IGC_RCTL_RST 0x00000001 /* Software reset */
213 #define IGC_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
214 #define IGC_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
216 #define IGC_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
229 #define IGC_CTRL_DEV_RST 0x20000000 /* Device reset */
230 #define IGC_CTRL_RST 0x04000000 /* Global reset */
234 #define IGC_CTRL_PHY_RST 0x80000000 /* PHY Reset */
255 #define IGC_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */
278 /* 1000/H is not supported, nor spec-compliant. */
328 #define IGC_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
345 /* GPY211 - I225 defines */
438 /* SW Semaphore Register */
461 #define IGC_ICR_DRSTA 0x40000000 /* Device Reset Asserted */
506 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
513 #define IGC_IMS_DRSTA IGC_ICR_DRSTA /* Device Reset Asserted */
551 #define IGC_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */
573 * Number of high/low register pairs in the RAR. The RAR (Receive Address
604 /* Loop limit on how long we wait for auto-negotiation to complete */
607 /* Number of 100 microseconds we wait for PCI Express master disable */
609 /* Number of milliseconds we wait for PHY configuration done after MAC reset */
611 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */
613 /* Number of milliseconds for NVM auto read done after MAC reset. */
626 #define IGC_TXCW_ANE 0x80000000 /* Auto-neg enable */
826 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
880 /* 1000BASE-T Control Register */
896 /* 1000BASE-T Status Register */
919 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
920 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
957 #define IGC_FLSECU_BLK_SW_ACCESS_I225 0x00000004 /* Block SW access */
1018 /* length of string needed to store PBA number */
1024 /* PBA (printed board assembly) number words */
1030 /* NVM Commands - Microwire */
1037 /* NVM Commands - SPI */
1041 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
1069 /* PCI/PCI-X/PCI-EX Config space */
1095 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
1120 #define M88IGC_PHY_PAGE_SELECT 0x1D /* Reg 29 for pg number setting */
1128 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
1139 * 1 = 50-80M
1140 * 2 = 80-110M
1141 * 3 = 110-140M
1152 /* Number of times we will attempt to autonegotiate before downshifting if we
1157 /* Number of times we will attempt to autonegotiate before downshifting if we
1170 * 15-5: page
1171 * 4-0: register offset
1189 /* Page 193 - Port Control Registers */
1194 /* Page 194 - KMRN Registers */
1208 #define IGC_N0_QUEUE -1
1230 /* DMA Coalescing BMC-to-OS Watchdog Enable */
1259 /* Minimum time for 1000BASE-T where no data will be transmit following move out
1263 /* Minimum time for 100BASE-T where no data will be transmit following move out
1351 #define IGC_FWSTS_FWRI 0x80000000 /* FW Reset Indication */
1353 #define IGC_VTCTRL_RST 0x04000000 /* Reset VF */