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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnuvoton,npcm7xx-pinctrl.txt3 The Nuvoton BMC NPCM7XX Pin Controller multi-function routed through
4 the multiplexing block, Each pin supports GPIO functionality (GPIOx)
9 - #address-cells : should be 1.
10 - #size-cells : should be 1.
11 - compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX.
12 - ranges : defines mapping ranges between pin controller node (parent)
17 The NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO.
19 Required GPIO Bank subnode-properties:
20 - reg : specifies physical base address and size of the GPIO
22 - gpio-controller : Marks the device node as a GPIO controller.
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H A Dnuvoton,npcm845-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nuvoton,npcm845-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tomer Maimon <tmaimon77@gmail.com>
13 The Nuvoton BMC NPCM8XX Pin Controller multi-function routed through
14 the multiplexing block, Each pin supports GPIO functionality (GPIOx)
20 const: nuvoton,npcm845-pinctrl
25 '#address-cells':
28 '#size-cells':
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H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
13 This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
37 mpp11 11 gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
38 ptp-2(trig)
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/linux/arch/arm/boot/dts/marvell/
H A Darmada-388-clearfog.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include "armada-388.dtsi"
9 #include "armada-38x-solidrun-microsom.dtsi"
13 /* So that mvebu u-boot can update the MAC addresses */
20 stdout-path = "serial0:115200n8";
23 reg_3p3v: regulator-3p3v {
24 compatible = "regulator-fixed";
25 regulator-name = "3P3V";
26 regulator-min-microvolt = <3300000>;
27 regulator-max-microvolt = <3300000>;
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/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-cf.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
19 reg_usb3_vbus0: regulator-usb3-vbus0 {
20 compatible = "regulator-fixed";
21 regulator-name = "vbus0";
22 regulator-min-microvolt = <5000000>;
23 regulator-max-microvolt = <5000000>;
29 i2c-bus = <&cp0_i2c1>;
30 los-gpios = <&expander0 12 GPIO_ACTIVE_HIGH>;
31 mod-def0-gpios = <&expander0 15 GPIO_ACTIVE_LOW>;
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/linux/Documentation/devicetree/bindings/pci/
H A Dbrcm,stb-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/brcm,stb-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jim Quinlan <james.quinlan@broadcom.com>
15 - enum:
16 - brcm,bcm2711-pcie # The Raspberry Pi 4
17 - brcm,bcm2712-pcie # Raspberry Pi 5
18 - brcm,bcm4908-pcie
19 - brcm,bcm7211-pcie # Broadcom STB version of RPi4
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H A Dnvidia,tegra194-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
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/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dtypes.h34 /* Board supports the Front End Module */
55 /* Flag to implement alternative A-band PLL settings */
59 /* Board supports the 2X4 diversity switch */
61 /* Board supports 5G band power gain */
63 /* Board overrides ASPM and Clkreq settings */
68 /* Board has a WAR for clock-harmonic spurs */
70 /* Flag to narrow G-band PLL loop b/w */
74 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
76 /* Flag to widen G-band PLL loop b/w */
86 * board specific GPIO assignment, gpio 0-3 are also customer-configurable
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/linux/drivers/net/wireless/realtek/rtw88/
H A Dpci.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2018-2019 Realtek Corporation
47 return skb->priority; in rtw_pci_get_tx_qsel()
53 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read8()
55 return readb(rtwpci->mmap + addr); in rtw_pci_read8()
60 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read16()
62 return readw(rtwpci->mmap + addr); in rtw_pci_read16()
67 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_read32()
69 return readl(rtwpci->mmap + addr); in rtw_pci_read32()
74 struct rtw_pci *rtwpci = (struct rtw_pci *)rtwdev->priv; in rtw_pci_write8()
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/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2019-2022 NVIDIA Corporation.
33 #include "pcie-designware.h"
35 #include <soc/tegra/bpmp-abi.h>
296 writel_relaxed(value, pcie->appl_base + reg); in appl_writel()
301 return readl_relaxed(pcie->appl_base + reg); in appl_readl()
306 struct dw_pcie *pci = &pcie->pci; in tegra_pcie_icc_set()
309 val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA); in tegra_pcie_icc_set()
316 if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0)) in tegra_pcie_icc_set()
317 dev_err(pcie->dev, "can't set bw[%u]\n", val); in tegra_pcie_icc_set()
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/linux/include/linux/ssb/
H A Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
226 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
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/linux/drivers/net/wireless/broadcom/b43/
H A Db43.h1 /* SPDX-License-Identifier: GPL-2.0 */
61 /* 32-bit DMA */
68 /* 64-bit DMA */
179 #define B43_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
181 #define B43_BFL_FEM 0x0800 /* supports the Front End Module */
203 #define B43_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
206 #define B43_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
207 #define B43_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
209 #define B43_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
211 #define B43_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
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/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c7 * Copyright (C) 2005-2016 Broadcom Corporation.
8 * Copyright (C) 2016-2017 Broadcom Limited.
14 * Copyright (C) 2000-2016 Broadcom Corporation.
15 * Copyright (C) 2016-2017 Broadcom Ltd.
52 #include <linux/dma-mapping.h>
56 #include <linux/hwmon-sysfs.h>
94 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
96 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
98 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
124 * and dev->tx_timeout() should be called to fix the problem
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