xref: /linux/arch/arm/boot/dts/marvell/armada-388-clearfog.dtsi (revision cdd5b5a9761fd66d17586e4f4ba6588c70e640ea) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Device Tree include file for SolidRun Clearfog 88F6828 based boards
4 *
5 *  Copyright (C) 2015 Russell King
6 */
7
8#include "armada-388.dtsi"
9#include "armada-38x-solidrun-microsom.dtsi"
10
11/ {
12	aliases {
13		/* So that mvebu u-boot can update the MAC addresses */
14		ethernet1 = &eth0;
15		ethernet2 = &eth1;
16		ethernet3 = &eth2;
17	};
18
19	chosen {
20		stdout-path = "serial0:115200n8";
21	};
22
23	reg_3p3v: regulator-3p3v {
24		compatible = "regulator-fixed";
25		regulator-name = "3P3V";
26		regulator-min-microvolt = <3300000>;
27		regulator-max-microvolt = <3300000>;
28		regulator-always-on;
29	};
30
31	soc {
32		internal-regs {
33			sata@a8000 {
34				/* pinctrl? */
35				status = "okay";
36			};
37
38			sata@e0000 {
39				/* pinctrl? */
40				status = "okay";
41			};
42
43			sdhci@d8000 {
44				bus-width = <4>;
45				cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
46				no-1-8-v;
47				pinctrl-0 = <&microsom_sdhci_pins
48					     &clearfog_sdhci_cd_pins>;
49				pinctrl-names = "default";
50				status = "okay";
51				vmmc-supply = <&reg_3p3v>;
52				wp-inverted;
53			};
54
55			usb@58000 {
56				/* CON3, nearest  power. */
57				status = "okay";
58			};
59
60			usb3@f8000 {
61				/* CON7 */
62				status = "okay";
63			};
64		};
65
66		pcie {
67			status = "okay";
68			/*
69			 * The two PCIe units are accessible through
70			 * the mini-PCIe connectors on the board.
71			 */
72			pcie@2,0 {
73				/* Port 1, Lane 0. CON3, nearest power. */
74				reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
75				status = "okay";
76			};
77		};
78	};
79
80	sfp: sfp {
81		compatible = "sff,sfp";
82		i2c-bus = <&i2c1>;
83		los-gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
84		mod-def0-gpio = <&expander0 15 GPIO_ACTIVE_LOW>;
85		tx-disable-gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
86		tx-fault-gpio = <&expander0 13 GPIO_ACTIVE_HIGH>;
87		maximum-power-milliwatt = <2000>;
88	};
89};
90
91&eth1 {
92	/* ethernet@30000 */
93	bm,pool-long = <2>;
94	bm,pool-short = <1>;
95	buffer-manager = <&bm>;
96	phys = <&comphy1 1>;
97	phy-mode = "sgmii";
98	status = "okay";
99};
100
101&eth2 {
102	/* ethernet@34000 */
103	bm,pool-long = <3>;
104	bm,pool-short = <1>;
105	buffer-manager = <&bm>;
106	managed = "in-band-status";
107	phys = <&comphy5 2>;
108	phy-mode = "sgmii";
109	sfp = <&sfp>;
110	status = "okay";
111};
112
113&i2c0 {
114	/*
115	 * PCA9655 GPIO expander, up to 1MHz clock.
116	 *  0-CON3 CLKREQ#
117	 *  1-CON3 PERST#
118	 *  2-
119	 *  3-CON3 W_DISABLE
120	 *  4-
121	 *  5-USB3 overcurrent
122	 *  6-USB3 power
123	 *  7-
124	 *  8-JP4 P1
125	 *  9-JP4 P4
126	 * 10-JP4 P5
127	 * 11-m.2 DEVSLP
128	 * 12-SFP_LOS
129	 * 13-SFP_TX_FAULT
130	 * 14-SFP_TX_DISABLE
131	 * 15-SFP_MOD_DEF0
132	 */
133	expander0: gpio-expander@20 {
134		/*
135		 * This is how it should be:
136		 * compatible = "onnn,pca9655", "nxp,pca9555";
137		 * but you can't do this because of the way I2C works.
138		 */
139		compatible = "nxp,pca9555";
140		gpio-controller;
141		#gpio-cells = <2>;
142		reg = <0x20>;
143
144		pcie1-0-clkreq-hog {
145			gpio-hog;
146			gpios = <0 GPIO_ACTIVE_LOW>;
147			input;
148			line-name = "pcie1.0-clkreq";
149		};
150		pcie1-0-w-disable-hog {
151			gpio-hog;
152			gpios = <3 GPIO_ACTIVE_LOW>;
153			output-low;
154			line-name = "pcie1.0-w-disable";
155		};
156		usb3-ilimit-hog {
157			gpio-hog;
158			gpios = <5 GPIO_ACTIVE_LOW>;
159			input;
160			line-name = "usb3-current-limit";
161		};
162		usb3-power-hog {
163			gpio-hog;
164			gpios = <6 GPIO_ACTIVE_HIGH>;
165			output-high;
166			line-name = "usb3-power";
167		};
168		m2-devslp-hog {
169			gpio-hog;
170			gpios = <11 GPIO_ACTIVE_HIGH>;
171			output-low;
172			line-name = "m.2 devslp";
173		};
174	};
175
176	/* The MCP3021 supports standard and fast modes */
177	mikrobus_adc: mcp3021@4c {
178		compatible = "microchip,mcp3021";
179		reg = <0x4c>;
180	};
181
182	eeprom@52 {
183		compatible = "atmel,24c02";
184		reg = <0x52>;
185		pagesize = <16>;
186	};
187};
188
189&i2c1 {
190	/*
191	 * Routed to SFP, mikrobus, and PCIe.
192	 * SFP limits this to 100kHz, and requires an AT24C01A/02/04 with
193	 *  address pins tied low, which takes addresses 0x50 and 0x51.
194	 * Mikrobus doesn't specify beyond an I2C bus being present.
195	 * PCIe uses ARP to assign addresses, or 0x63-0x64.
196	 */
197	clock-frequency = <100000>;
198	pinctrl-0 = <&clearfog_i2c1_pins>;
199	pinctrl-names = "default";
200	status = "okay";
201};
202
203&pinctrl {
204	clearfog_i2c1_pins: i2c1-pins {
205		/* SFP, PCIe, mSATA, mikrobus */
206		marvell,pins = "mpp26", "mpp27";
207		marvell,function = "i2c1";
208	};
209	clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
210		marvell,pins = "mpp20";
211		marvell,function = "gpio";
212	};
213	mikro_pins: mikro-pins {
214		/* int: mpp22 rst: mpp29 */
215		marvell,pins = "mpp22", "mpp29";
216		marvell,function = "gpio";
217	};
218	mikro_spi_pins: mikro-spi-pins {
219		marvell,pins = "mpp43";
220		marvell,function = "spi1";
221	};
222	mikro_uart_pins: mikro-uart-pins {
223		marvell,pins = "mpp24", "mpp25";
224		marvell,function = "ua1";
225	};
226};
227
228&spi1 {
229	/*
230	 * Add SPI CS pins for clearfog:
231	 * CS0: W25Q32
232	 * CS1: PIC microcontroller (Pro models)
233	 * CS2: mikrobus
234	 */
235	pinctrl-0 = <&spi1_pins &mikro_spi_pins>;
236	pinctrl-names = "default";
237	status = "okay";
238};
239
240&uart1 {
241	/* mikrobus uart */
242	pinctrl-0 = <&mikro_uart_pins>;
243	pinctrl-names = "default";
244	status = "okay";
245};
246