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Searched +full:stih407 +full:- +full:usb2 +full:- +full:phy (Results 1 – 10 of 10) sorted by relevance

/linux/Documentation/devicetree/bindings/phy/
H A Dst,stih407-usb2-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/st,stih407-usb2-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STiH407 USB PHY controller
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 The USB picoPHY device is the PHY for both USB2 and USB3 host controllers
14 (when controlling usb2/1.1 devices) available on STiH407 SoC family from
19 const: st,stih407-usb2-phy
23 $ref: /schemas/types.yaml#/definitions/phandle-array
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/linux/drivers/phy/st/
H A Dphy-stih407-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * STMicroelectronics Generic PHY driver for STiH407 USB2.
19 #include <linux/phy/phy.h>
33 struct phy *phy; member
44 reset_control_deassert(phy_dev->rstc); in stih407_usb2_pico_ctrl()
46 return regmap_update_bits(phy_dev->regmap, phy_dev->ctrl, in stih407_usb2_pico_ctrl()
51 static int stih407_usb2_init_port(struct phy *phy) in stih407_usb2_init_port() argument
54 struct stih407_usb2_picophy *phy_dev = phy_get_drvdata(phy); in stih407_usb2_init_port()
58 ret = regmap_update_bits(phy_dev->regmap, in stih407_usb2_init_port()
59 phy_dev->param, in stih407_usb2_init_port()
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/linux/arch/arm/boot/dts/st/
H A Dstih410.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih410-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
16 compatible = "st,stih407-usb2-phy";
17 #phy-cells = <0>;
21 reset-names = "global", "port";
27 compatible = "st,stih407-usb2-phy";
28 #phy-cells = <0>;
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H A Dstih418.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih418-clock.dtsi"
7 #include "stih407-family.dtsi"
8 #include "stih410-pinctrl.dtsi"
9 #include <dt-bindings/thermal/thermal.h>
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
18 /* u-boot puts hpen in SBC dmem at 0xa4 offset */
19 cpu-release-addr = <0x94100A4>;
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H A Dstih407-family.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "stih407-pinctrl.dtsi"
7 #include <dt-bindings/mfd/st-lpc.h>
8 #include <dt-bindings/phy/phy.h>
9 #include <dt-bindings/reset/stih407-resets.h>
10 #include <dt-bindings/interrupt-controller/irq-st.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 reserved-memory {
16 #address-cells = <1>;
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/linux/Documentation/devicetree/bindings/usb/
H A Ddwc3-st.txt3 This file documents the parameters for the dwc3-st driver.
5 STiH407 based platforms.
8 - compatible : must be "st,stih407-dwc3"
9 - reg : glue logic base address and USB syscfg ctrl register offset
10 - reg-names : should be "reg-glue" and "syscfg-reg"
11 - st,syscon : should be phandle to system configuration node which
13 - resets : list of phandle and reset specifier pairs. There should be two entries, one
15 - reset-names : list of reset signal names. Names should be "powerdown" and "softreset"
16 See: Documentation/devicetree/bindings/reset/st,stih407-powerdown.yaml
19 - #address-cells, #size-cells : should be '1' if the device has sub-nodes
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/linux/Documentation/devicetree/bindings/reset/
H A Dst,stih407-picophyreset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/st,stih407-picophyreset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
14 disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in
24 const: st,stih407-picophyreset
26 '#reset-cells':
30 - compatible
31 - '#reset-cells'
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/linux/drivers/usb/dwc3/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
19 bool "Register ULPI PHY Interface"
22 Select this if you have ULPI type PHY attached to your DWC3
64 AM437x use this IP for USB2/3 functionality.
78 tristate "PCIe-based Platforms"
86 tristate "Synopsys PCIe-based HAPS Platforms"
98 Support of USB2/3 functionality in TI Keystone2 and AM654 platforms.
109 Support USB2/3 functionality in Amlogic G12A platforms.
117 Support USB2/3 functionality in simple SoC integrations.
127 inside (i.e. STiH407).
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/linux/drivers/clk/st/
H A Dclk-flexgen.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * clk-flexgen.c
5 * Copyright (C) ST-Microelectronics SA 2013
6 * Author: Maxime Coquelin <maxime.coquelin@st.com> for ST-Microelectronics.
10 #include <linux/clk-provider.h>
36 /* Pre-divisor's gate */
38 /* Pre-divisor */
56 struct clk_hw *pgate_hw = &flexgen->pgate.hw; in flexgen_enable()
57 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_enable()
73 struct clk_hw *fgate_hw = &flexgen->fgate.hw; in flexgen_disable()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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