1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2724ba675SRob Herring/* 3724ba675SRob Herring * Copyright (C) 2014 STMicroelectronics Limited. 4724ba675SRob Herring * Author: Peter Griffin <peter.griffin@linaro.org> 5724ba675SRob Herring */ 6724ba675SRob Herring#include "stih418-clock.dtsi" 7724ba675SRob Herring#include "stih407-family.dtsi" 8724ba675SRob Herring#include "stih410-pinctrl.dtsi" 9*b664f6f7SRaphael Gallais-Pou#include <dt-bindings/thermal/thermal.h> 10724ba675SRob Herring/ { 11724ba675SRob Herring cpus { 12724ba675SRob Herring #address-cells = <1>; 13724ba675SRob Herring #size-cells = <0>; 14*b664f6f7SRaphael Gallais-Pou cpu2: cpu@2 { 15724ba675SRob Herring device_type = "cpu"; 16724ba675SRob Herring compatible = "arm,cortex-a9"; 17724ba675SRob Herring reg = <2>; 18724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 19724ba675SRob Herring cpu-release-addr = <0x94100A4>; 20*b664f6f7SRaphael Gallais-Pou #cooling-cells = <2>; 21724ba675SRob Herring }; 22*b664f6f7SRaphael Gallais-Pou cpu3: cpu@3 { 23724ba675SRob Herring device_type = "cpu"; 24724ba675SRob Herring compatible = "arm,cortex-a9"; 25724ba675SRob Herring reg = <3>; 26724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 27724ba675SRob Herring cpu-release-addr = <0x94100A4>; 28*b664f6f7SRaphael Gallais-Pou #cooling-cells = <2>; 29724ba675SRob Herring }; 30724ba675SRob Herring }; 31724ba675SRob Herring 32724ba675SRob Herring usb2_picophy1: phy2 { 33724ba675SRob Herring compatible = "st,stih407-usb2-phy"; 34724ba675SRob Herring #phy-cells = <0>; 35724ba675SRob Herring st,syscfg = <&syscfg_core 0xf8 0xf4>; 36724ba675SRob Herring resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 37724ba675SRob Herring <&picophyreset STIH407_PICOPHY0_RESET>; 38724ba675SRob Herring reset-names = "global", "port"; 39724ba675SRob Herring }; 40724ba675SRob Herring 41724ba675SRob Herring usb2_picophy2: phy3 { 42724ba675SRob Herring compatible = "st,stih407-usb2-phy"; 43724ba675SRob Herring #phy-cells = <0>; 44724ba675SRob Herring st,syscfg = <&syscfg_core 0xfc 0xf4>; 45724ba675SRob Herring resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 46724ba675SRob Herring <&picophyreset STIH407_PICOPHY1_RESET>; 47724ba675SRob Herring reset-names = "global", "port"; 48724ba675SRob Herring }; 49724ba675SRob Herring 50*b664f6f7SRaphael Gallais-Pou thermal-zones { 51*b664f6f7SRaphael Gallais-Pou cpu_thermal: cpu-thermal { 52*b664f6f7SRaphael Gallais-Pou polling-delay-passive = <250>; /* 250ms */ 53*b664f6f7SRaphael Gallais-Pou polling-delay = <1000>; /* 1000ms */ 54*b664f6f7SRaphael Gallais-Pou 55*b664f6f7SRaphael Gallais-Pou thermal-sensors = <&thermal>; 56*b664f6f7SRaphael Gallais-Pou 57*b664f6f7SRaphael Gallais-Pou trips { 58*b664f6f7SRaphael Gallais-Pou cpu_crit: cpu-crit { 59*b664f6f7SRaphael Gallais-Pou temperature = <95000>; /* 95C */ 60*b664f6f7SRaphael Gallais-Pou hysteresis = <2000>; 61*b664f6f7SRaphael Gallais-Pou type = "critical"; 62*b664f6f7SRaphael Gallais-Pou }; 63*b664f6f7SRaphael Gallais-Pou cpu_alert: cpu-alert { 64*b664f6f7SRaphael Gallais-Pou temperature = <85000>; /* 85C */ 65*b664f6f7SRaphael Gallais-Pou hysteresis = <2000>; 66*b664f6f7SRaphael Gallais-Pou type = "passive"; 67*b664f6f7SRaphael Gallais-Pou }; 68*b664f6f7SRaphael Gallais-Pou }; 69*b664f6f7SRaphael Gallais-Pou 70*b664f6f7SRaphael Gallais-Pou cooling-maps { 71*b664f6f7SRaphael Gallais-Pou map { 72*b664f6f7SRaphael Gallais-Pou trip = <&cpu_alert>; 73*b664f6f7SRaphael Gallais-Pou cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 74*b664f6f7SRaphael Gallais-Pou <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 75*b664f6f7SRaphael Gallais-Pou <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 76*b664f6f7SRaphael Gallais-Pou <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 77*b664f6f7SRaphael Gallais-Pou }; 78*b664f6f7SRaphael Gallais-Pou }; 79*b664f6f7SRaphael Gallais-Pou }; 80*b664f6f7SRaphael Gallais-Pou }; 81*b664f6f7SRaphael Gallais-Pou 82724ba675SRob Herring soc { 83724ba675SRob Herring rng11: rng@8a8a000 { 84724ba675SRob Herring status = "disabled"; 85724ba675SRob Herring }; 86724ba675SRob Herring 87724ba675SRob Herring ohci0: usb@9a03c00 { 88724ba675SRob Herring compatible = "st,st-ohci-300x"; 89724ba675SRob Herring reg = <0x9a03c00 0x100>; 90724ba675SRob Herring interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 91724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 92724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, 93724ba675SRob Herring <&softreset STIH407_USB2_PORT0_SOFTRESET>; 94724ba675SRob Herring reset-names = "power", "softreset"; 95724ba675SRob Herring phys = <&usb2_picophy1>; 96724ba675SRob Herring phy-names = "usb"; 97724ba675SRob Herring }; 98724ba675SRob Herring 99724ba675SRob Herring ehci0: usb@9a03e00 { 100724ba675SRob Herring compatible = "st,st-ehci-300x"; 101724ba675SRob Herring reg = <0x9a03e00 0x100>; 102724ba675SRob Herring interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 103724ba675SRob Herring pinctrl-names = "default"; 104724ba675SRob Herring pinctrl-0 = <&pinctrl_usb0>; 105724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 106724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>, 107724ba675SRob Herring <&softreset STIH407_USB2_PORT0_SOFTRESET>; 108724ba675SRob Herring reset-names = "power", "softreset"; 109724ba675SRob Herring phys = <&usb2_picophy1>; 110724ba675SRob Herring phy-names = "usb"; 111724ba675SRob Herring }; 112724ba675SRob Herring 113724ba675SRob Herring ohci1: usb@9a83c00 { 114724ba675SRob Herring compatible = "st,st-ohci-300x"; 115724ba675SRob Herring reg = <0x9a83c00 0x100>; 116724ba675SRob Herring interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 117724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 118724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, 119724ba675SRob Herring <&softreset STIH407_USB2_PORT1_SOFTRESET>; 120724ba675SRob Herring reset-names = "power", "softreset"; 121724ba675SRob Herring phys = <&usb2_picophy2>; 122724ba675SRob Herring phy-names = "usb"; 123724ba675SRob Herring }; 124724ba675SRob Herring 125724ba675SRob Herring ehci1: usb@9a83e00 { 126724ba675SRob Herring compatible = "st,st-ehci-300x"; 127724ba675SRob Herring reg = <0x9a83e00 0x100>; 128724ba675SRob Herring interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 129724ba675SRob Herring pinctrl-names = "default"; 130724ba675SRob Herring pinctrl-0 = <&pinctrl_usb1>; 131724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>; 132724ba675SRob Herring resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>, 133724ba675SRob Herring <&softreset STIH407_USB2_PORT1_SOFTRESET>; 134724ba675SRob Herring reset-names = "power", "softreset"; 135724ba675SRob Herring phys = <&usb2_picophy2>; 136724ba675SRob Herring phy-names = "usb"; 137724ba675SRob Herring }; 138724ba675SRob Herring 139724ba675SRob Herring mmc0: sdhci@9060000 { 140724ba675SRob Herring assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>; 141724ba675SRob Herring assigned-clock-parents = <&clk_s_c0_pll1 0>; 142724ba675SRob Herring assigned-clock-rates = <200000000>; 143724ba675SRob Herring }; 144724ba675SRob Herring 145*b664f6f7SRaphael Gallais-Pou thermal: thermal@91a0000 { 146724ba675SRob Herring compatible = "st,stih407-thermal"; 147724ba675SRob Herring reg = <0x91a0000 0x28>; 148724ba675SRob Herring clock-names = "thermal"; 149724ba675SRob Herring clocks = <&clk_sysin>; 150724ba675SRob Herring interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; 151e00d100aSRaphael Gallais-Pou #thermal-sensor-cells = <0>; 152724ba675SRob Herring }; 153724ba675SRob Herring }; 154724ba675SRob Herring}; 155