1724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2724ba675SRob Herring/* 3724ba675SRob Herring * Copyright (C) 2014 STMicroelectronics Limited. 4724ba675SRob Herring * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 5724ba675SRob Herring */ 6724ba675SRob Herring#include "stih407-pinctrl.dtsi" 7724ba675SRob Herring#include <dt-bindings/mfd/st-lpc.h> 8724ba675SRob Herring#include <dt-bindings/phy/phy.h> 9724ba675SRob Herring#include <dt-bindings/reset/stih407-resets.h> 10724ba675SRob Herring#include <dt-bindings/interrupt-controller/irq-st.h> 11724ba675SRob Herring/ { 12724ba675SRob Herring #address-cells = <1>; 13724ba675SRob Herring #size-cells = <1>; 14724ba675SRob Herring 15724ba675SRob Herring reserved-memory { 16724ba675SRob Herring #address-cells = <1>; 17724ba675SRob Herring #size-cells = <1>; 18724ba675SRob Herring ranges; 19724ba675SRob Herring 20724ba675SRob Herring gp0_reserved: rproc@45000000 { 21724ba675SRob Herring compatible = "shared-dma-pool"; 22724ba675SRob Herring reg = <0x45000000 0x00400000>; 23724ba675SRob Herring no-map; 24724ba675SRob Herring }; 25724ba675SRob Herring 26724ba675SRob Herring delta_reserved: rproc@44000000 { 27724ba675SRob Herring compatible = "shared-dma-pool"; 28724ba675SRob Herring reg = <0x44000000 0x01000000>; 29724ba675SRob Herring no-map; 30724ba675SRob Herring }; 31724ba675SRob Herring }; 32724ba675SRob Herring 33724ba675SRob Herring cpus { 34724ba675SRob Herring #address-cells = <1>; 35724ba675SRob Herring #size-cells = <0>; 36*b664f6f7SRaphael Gallais-Pou cpu0: cpu@0 { 37724ba675SRob Herring device_type = "cpu"; 38724ba675SRob Herring compatible = "arm,cortex-a9"; 39724ba675SRob Herring reg = <0>; 40724ba675SRob Herring 41724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 42724ba675SRob Herring cpu-release-addr = <0x94100A4>; 43724ba675SRob Herring 44724ba675SRob Herring /* kHz uV */ 45724ba675SRob Herring operating-points = <1500000 0 46724ba675SRob Herring 1200000 0 47724ba675SRob Herring 800000 0 48724ba675SRob Herring 500000 0>; 49724ba675SRob Herring 50724ba675SRob Herring clocks = <&clk_m_a9>; 51724ba675SRob Herring clock-names = "cpu"; 52724ba675SRob Herring clock-latency = <100000>; 53724ba675SRob Herring cpu0-supply = <&pwm_regulator>; 54724ba675SRob Herring st,syscfg = <&syscfg_core 0x8e0>; 55*b664f6f7SRaphael Gallais-Pou #cooling-cells = <2>; 56724ba675SRob Herring }; 57*b664f6f7SRaphael Gallais-Pou cpu1: cpu@1 { 58724ba675SRob Herring device_type = "cpu"; 59724ba675SRob Herring compatible = "arm,cortex-a9"; 60724ba675SRob Herring reg = <1>; 61724ba675SRob Herring 62724ba675SRob Herring /* u-boot puts hpen in SBC dmem at 0xa4 offset */ 63724ba675SRob Herring cpu-release-addr = <0x94100A4>; 64724ba675SRob Herring 65724ba675SRob Herring /* kHz uV */ 66724ba675SRob Herring operating-points = <1500000 0 67724ba675SRob Herring 1200000 0 68724ba675SRob Herring 800000 0 69724ba675SRob Herring 500000 0>; 70*b664f6f7SRaphael Gallais-Pou #cooling-cells = <2>; 71724ba675SRob Herring }; 72724ba675SRob Herring }; 73724ba675SRob Herring 74724ba675SRob Herring intc: interrupt-controller@8761000 { 75724ba675SRob Herring compatible = "arm,cortex-a9-gic"; 76724ba675SRob Herring #interrupt-cells = <3>; 77724ba675SRob Herring interrupt-controller; 78724ba675SRob Herring reg = <0x08761000 0x1000>, <0x08760100 0x100>; 79724ba675SRob Herring }; 80724ba675SRob Herring 81724ba675SRob Herring scu@8760000 { 82724ba675SRob Herring compatible = "arm,cortex-a9-scu"; 83724ba675SRob Herring reg = <0x08760000 0x1000>; 84724ba675SRob Herring }; 85724ba675SRob Herring 86724ba675SRob Herring timer@8760200 { 87724ba675SRob Herring interrupt-parent = <&intc>; 88724ba675SRob Herring compatible = "arm,cortex-a9-global-timer"; 89724ba675SRob Herring reg = <0x08760200 0x100>; 90724ba675SRob Herring interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 91724ba675SRob Herring clocks = <&arm_periph_clk>; 92724ba675SRob Herring }; 93724ba675SRob Herring 94724ba675SRob Herring l2: cache-controller@8762000 { 95724ba675SRob Herring compatible = "arm,pl310-cache"; 96724ba675SRob Herring reg = <0x08762000 0x1000>; 97724ba675SRob Herring arm,data-latency = <3 3 3>; 98724ba675SRob Herring arm,tag-latency = <2 2 2>; 99724ba675SRob Herring cache-unified; 100724ba675SRob Herring cache-level = <2>; 101724ba675SRob Herring }; 102724ba675SRob Herring 103724ba675SRob Herring arm-pmu { 104724ba675SRob Herring interrupt-parent = <&intc>; 105724ba675SRob Herring compatible = "arm,cortex-a9-pmu"; 106724ba675SRob Herring interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 107724ba675SRob Herring }; 108724ba675SRob Herring 109724ba675SRob Herring pwm_regulator: pwm-regulator { 110724ba675SRob Herring compatible = "pwm-regulator"; 111724ba675SRob Herring pwms = <&pwm1 3 8448>; 112724ba675SRob Herring regulator-name = "CPU_1V0_AVS"; 113724ba675SRob Herring regulator-min-microvolt = <784000>; 114724ba675SRob Herring regulator-max-microvolt = <1299000>; 115724ba675SRob Herring regulator-always-on; 116724ba675SRob Herring status = "okay"; 117724ba675SRob Herring }; 118724ba675SRob Herring 119724ba675SRob Herring restart: restart-controller { 120724ba675SRob Herring compatible = "st,stih407-restart"; 121724ba675SRob Herring st,syscfg = <&syscfg_sbc_reg>; 122724ba675SRob Herring status = "okay"; 123724ba675SRob Herring }; 124724ba675SRob Herring 125724ba675SRob Herring powerdown: powerdown-controller { 126724ba675SRob Herring compatible = "st,stih407-powerdown"; 127724ba675SRob Herring #reset-cells = <1>; 128724ba675SRob Herring }; 129724ba675SRob Herring 130724ba675SRob Herring softreset: softreset-controller { 131724ba675SRob Herring compatible = "st,stih407-softreset"; 132724ba675SRob Herring #reset-cells = <1>; 133724ba675SRob Herring }; 134724ba675SRob Herring 135724ba675SRob Herring picophyreset: picophyreset-controller { 136724ba675SRob Herring compatible = "st,stih407-picophyreset"; 137724ba675SRob Herring #reset-cells = <1>; 138724ba675SRob Herring }; 139724ba675SRob Herring 140724ba675SRob Herring irq-syscfg { 141724ba675SRob Herring compatible = "st,stih407-irq-syscfg"; 142724ba675SRob Herring st,syscfg = <&syscfg_core>; 143724ba675SRob Herring st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, 144724ba675SRob Herring <ST_IRQ_SYSCFG_PMU_1>; 145724ba675SRob Herring st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, 146724ba675SRob Herring <ST_IRQ_SYSCFG_DISABLED>; 147724ba675SRob Herring }; 148724ba675SRob Herring 149724ba675SRob Herring usb2_picophy0: phy1 { 150724ba675SRob Herring compatible = "st,stih407-usb2-phy"; 151724ba675SRob Herring #phy-cells = <0>; 152724ba675SRob Herring st,syscfg = <&syscfg_core 0x100 0xf4>; 153724ba675SRob Herring resets = <&softreset STIH407_PICOPHY_SOFTRESET>, 154724ba675SRob Herring <&picophyreset STIH407_PICOPHY2_RESET>; 155724ba675SRob Herring reset-names = "global", "port"; 156724ba675SRob Herring }; 157724ba675SRob Herring 158724ba675SRob Herring miphy28lp_phy: miphy28lp { 159724ba675SRob Herring compatible = "st,miphy28lp-phy"; 160724ba675SRob Herring st,syscfg = <&syscfg_core>; 161724ba675SRob Herring #address-cells = <1>; 162724ba675SRob Herring #size-cells = <1>; 163724ba675SRob Herring ranges; 164724ba675SRob Herring 165724ba675SRob Herring phy_port0: port@9b22000 { 166724ba675SRob Herring reg = <0x9b22000 0xff>, 167724ba675SRob Herring <0x9b09000 0xff>, 168724ba675SRob Herring <0x9b04000 0xff>; 169724ba675SRob Herring reg-names = "sata-up", 170724ba675SRob Herring "pcie-up", 171724ba675SRob Herring "pipew"; 172724ba675SRob Herring 173724ba675SRob Herring st,syscfg = <0x114 0x818 0xe0 0xec>; 174724ba675SRob Herring #phy-cells = <1>; 175724ba675SRob Herring 176724ba675SRob Herring reset-names = "miphy-sw-rst"; 177724ba675SRob Herring resets = <&softreset STIH407_MIPHY0_SOFTRESET>; 178724ba675SRob Herring }; 179724ba675SRob Herring 180724ba675SRob Herring phy_port1: port@9b2a000 { 181724ba675SRob Herring reg = <0x9b2a000 0xff>, 182724ba675SRob Herring <0x9b19000 0xff>, 183724ba675SRob Herring <0x9b14000 0xff>; 184724ba675SRob Herring reg-names = "sata-up", 185724ba675SRob Herring "pcie-up", 186724ba675SRob Herring "pipew"; 187724ba675SRob Herring 188724ba675SRob Herring st,syscfg = <0x118 0x81c 0xe4 0xf0>; 189724ba675SRob Herring 190724ba675SRob Herring #phy-cells = <1>; 191724ba675SRob Herring 192724ba675SRob Herring reset-names = "miphy-sw-rst"; 193724ba675SRob Herring resets = <&softreset STIH407_MIPHY1_SOFTRESET>; 194724ba675SRob Herring }; 195724ba675SRob Herring 196724ba675SRob Herring phy_port2: port@8f95000 { 197724ba675SRob Herring reg = <0x8f95000 0xff>, 198724ba675SRob Herring <0x8f90000 0xff>; 199724ba675SRob Herring reg-names = "pipew", 200724ba675SRob Herring "usb3-up"; 201724ba675SRob Herring 202724ba675SRob Herring st,syscfg = <0x11c 0x820>; 203724ba675SRob Herring 204724ba675SRob Herring #phy-cells = <1>; 205724ba675SRob Herring 206724ba675SRob Herring reset-names = "miphy-sw-rst"; 207724ba675SRob Herring resets = <&softreset STIH407_MIPHY2_SOFTRESET>; 208724ba675SRob Herring }; 209724ba675SRob Herring }; 210724ba675SRob Herring 211724ba675SRob Herring st231_gp0: st231-gp0 { 212724ba675SRob Herring compatible = "st,st231-rproc"; 213724ba675SRob Herring memory-region = <&gp0_reserved>; 214724ba675SRob Herring resets = <&softreset STIH407_ST231_GP0_SOFTRESET>; 215724ba675SRob Herring reset-names = "sw_reset"; 216724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ST231_GP_0>; 217724ba675SRob Herring clock-frequency = <600000000>; 218724ba675SRob Herring st,syscfg = <&syscfg_core 0x22c>; 219724ba675SRob Herring #mbox-cells = <1>; 220724ba675SRob Herring mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 221724ba675SRob Herring mboxes = <&mailbox0 0 2>, <&mailbox2 0 1>, <&mailbox0 0 3>, <&mailbox2 0 0>; 222724ba675SRob Herring }; 223724ba675SRob Herring 224724ba675SRob Herring st231_delta: st231-delta { 225724ba675SRob Herring compatible = "st,st231-rproc"; 226724ba675SRob Herring memory-region = <&delta_reserved>; 227724ba675SRob Herring resets = <&softreset STIH407_ST231_DMU_SOFTRESET>; 228724ba675SRob Herring reset-names = "sw_reset"; 229724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ST231_DMU>; 230724ba675SRob Herring clock-frequency = <600000000>; 231724ba675SRob Herring st,syscfg = <&syscfg_core 0x224>; 232724ba675SRob Herring #mbox-cells = <1>; 233724ba675SRob Herring mbox-names = "vq0_rx", "vq0_tx", "vq1_rx", "vq1_tx"; 234724ba675SRob Herring mboxes = <&mailbox0 0 0>, <&mailbox3 0 1>, <&mailbox0 0 1>, <&mailbox3 0 0>; 235724ba675SRob Herring }; 236724ba675SRob Herring 237724ba675SRob Herring delta0 { 238724ba675SRob Herring compatible = "st,st-delta"; 239724ba675SRob Herring clock-names = "delta", 240724ba675SRob Herring "delta-st231", 241724ba675SRob Herring "delta-flash-promip"; 242724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_VID_DMU>, 243724ba675SRob Herring <&clk_s_c0_flexgen CLK_ST231_DMU>, 244724ba675SRob Herring <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 245724ba675SRob Herring }; 246724ba675SRob Herring 247724ba675SRob Herring soc { 248724ba675SRob Herring #address-cells = <1>; 249724ba675SRob Herring #size-cells = <1>; 250724ba675SRob Herring interrupt-parent = <&intc>; 251724ba675SRob Herring ranges; 252724ba675SRob Herring compatible = "simple-bus"; 253724ba675SRob Herring 254724ba675SRob Herring syscfg_sbc: sbc-syscfg@9620000 { 255724ba675SRob Herring compatible = "st,stih407-sbc-syscfg", "syscon"; 256724ba675SRob Herring reg = <0x9620000 0x1000>; 257724ba675SRob Herring }; 258724ba675SRob Herring 259724ba675SRob Herring syscfg_front: front-syscfg@9280000 { 260724ba675SRob Herring compatible = "st,stih407-front-syscfg", "syscon"; 261724ba675SRob Herring reg = <0x9280000 0x1000>; 262724ba675SRob Herring }; 263724ba675SRob Herring 264724ba675SRob Herring syscfg_rear: rear-syscfg@9290000 { 265724ba675SRob Herring compatible = "st,stih407-rear-syscfg", "syscon"; 266724ba675SRob Herring reg = <0x9290000 0x1000>; 267724ba675SRob Herring }; 268724ba675SRob Herring 269724ba675SRob Herring syscfg_flash: flash-syscfg@92a0000 { 270724ba675SRob Herring compatible = "st,stih407-flash-syscfg", "syscon"; 271724ba675SRob Herring reg = <0x92a0000 0x1000>; 272724ba675SRob Herring }; 273724ba675SRob Herring 274724ba675SRob Herring syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { 275724ba675SRob Herring compatible = "st,stih407-sbc-reg-syscfg", "syscon"; 276724ba675SRob Herring reg = <0x9600000 0x1000>; 277724ba675SRob Herring }; 278724ba675SRob Herring 279724ba675SRob Herring syscfg_core: core-syscfg@92b0000 { 280724ba675SRob Herring compatible = "st,stih407-core-syscfg", "syscon"; 281724ba675SRob Herring reg = <0x92b0000 0x1000>; 282724ba675SRob Herring 283724ba675SRob Herring sti_sasg_codec: sti-sasg-codec { 284724ba675SRob Herring compatible = "st,stih407-sas-codec"; 285724ba675SRob Herring #sound-dai-cells = <1>; 286724ba675SRob Herring status = "disabled"; 287724ba675SRob Herring st,syscfg = <&syscfg_core>; 288724ba675SRob Herring }; 289724ba675SRob Herring }; 290724ba675SRob Herring 291724ba675SRob Herring syscfg_lpm: lpm-syscfg@94b5100 { 292724ba675SRob Herring compatible = "st,stih407-lpm-syscfg", "syscon"; 293724ba675SRob Herring reg = <0x94b5100 0x1000>; 294724ba675SRob Herring }; 295724ba675SRob Herring 296724ba675SRob Herring /* Display */ 297724ba675SRob Herring vtg_main: sti-vtg-main@8d02800 { 298724ba675SRob Herring compatible = "st,vtg"; 299724ba675SRob Herring reg = <0x8d02800 0x200>; 300724ba675SRob Herring interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 301724ba675SRob Herring }; 302724ba675SRob Herring 303724ba675SRob Herring vtg_aux: sti-vtg-aux@8d00200 { 304724ba675SRob Herring compatible = "st,vtg"; 305724ba675SRob Herring reg = <0x8d00200 0x100>; 306724ba675SRob Herring interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 307724ba675SRob Herring }; 308724ba675SRob Herring 309724ba675SRob Herring serial@9830000 { 310724ba675SRob Herring compatible = "st,asc"; 311724ba675SRob Herring reg = <0x9830000 0x2c>; 312724ba675SRob Herring interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 313724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 314724ba675SRob Herring /* Pinctrl moved out to a per-board configuration */ 315724ba675SRob Herring 316724ba675SRob Herring status = "disabled"; 317724ba675SRob Herring }; 318724ba675SRob Herring 319724ba675SRob Herring serial@9831000 { 320724ba675SRob Herring compatible = "st,asc"; 321724ba675SRob Herring reg = <0x9831000 0x2c>; 322724ba675SRob Herring interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 323724ba675SRob Herring pinctrl-names = "default"; 324724ba675SRob Herring pinctrl-0 = <&pinctrl_serial1>; 325724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 326724ba675SRob Herring 327724ba675SRob Herring status = "disabled"; 328724ba675SRob Herring }; 329724ba675SRob Herring 330724ba675SRob Herring serial@9832000 { 331724ba675SRob Herring compatible = "st,asc"; 332724ba675SRob Herring reg = <0x9832000 0x2c>; 333724ba675SRob Herring interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 334724ba675SRob Herring pinctrl-names = "default"; 335724ba675SRob Herring pinctrl-0 = <&pinctrl_serial2>; 336724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 337724ba675SRob Herring 338724ba675SRob Herring status = "disabled"; 339724ba675SRob Herring }; 340724ba675SRob Herring 341724ba675SRob Herring /* SBC_ASC0 - UART10 */ 342724ba675SRob Herring sbc_serial0: serial@9530000 { 343724ba675SRob Herring compatible = "st,asc"; 344724ba675SRob Herring reg = <0x9530000 0x2c>; 345724ba675SRob Herring interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 346724ba675SRob Herring pinctrl-names = "default"; 347724ba675SRob Herring pinctrl-0 = <&pinctrl_sbc_serial0>; 348724ba675SRob Herring clocks = <&clk_sysin>; 349724ba675SRob Herring 350724ba675SRob Herring status = "disabled"; 351724ba675SRob Herring }; 352724ba675SRob Herring 353724ba675SRob Herring serial@9531000 { 354724ba675SRob Herring compatible = "st,asc"; 355724ba675SRob Herring reg = <0x9531000 0x2c>; 356724ba675SRob Herring interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 357724ba675SRob Herring pinctrl-names = "default"; 358724ba675SRob Herring pinctrl-0 = <&pinctrl_sbc_serial1>; 359724ba675SRob Herring clocks = <&clk_sysin>; 360724ba675SRob Herring 361724ba675SRob Herring status = "disabled"; 362724ba675SRob Herring }; 363724ba675SRob Herring 364724ba675SRob Herring i2c@9840000 { 365724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 366724ba675SRob Herring interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 367724ba675SRob Herring reg = <0x9840000 0x110>; 368724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 369724ba675SRob Herring clock-names = "ssc"; 370724ba675SRob Herring clock-frequency = <400000>; 371724ba675SRob Herring pinctrl-names = "default"; 372724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c0_default>; 373724ba675SRob Herring #address-cells = <1>; 374724ba675SRob Herring #size-cells = <0>; 375724ba675SRob Herring 376724ba675SRob Herring status = "disabled"; 377724ba675SRob Herring }; 378724ba675SRob Herring 379724ba675SRob Herring i2c@9841000 { 380724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 381724ba675SRob Herring reg = <0x9841000 0x110>; 382724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 383724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 384724ba675SRob Herring clock-names = "ssc"; 385724ba675SRob Herring clock-frequency = <400000>; 386724ba675SRob Herring pinctrl-names = "default"; 387724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c1_default>; 388724ba675SRob Herring #address-cells = <1>; 389724ba675SRob Herring #size-cells = <0>; 390724ba675SRob Herring 391724ba675SRob Herring status = "disabled"; 392724ba675SRob Herring }; 393724ba675SRob Herring 394724ba675SRob Herring i2c@9842000 { 395724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 396724ba675SRob Herring reg = <0x9842000 0x110>; 397724ba675SRob Herring interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 398724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 399724ba675SRob Herring clock-names = "ssc"; 400724ba675SRob Herring clock-frequency = <400000>; 401724ba675SRob Herring pinctrl-names = "default"; 402724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c2_default>; 403724ba675SRob Herring #address-cells = <1>; 404724ba675SRob Herring #size-cells = <0>; 405724ba675SRob Herring 406724ba675SRob Herring status = "disabled"; 407724ba675SRob Herring }; 408724ba675SRob Herring 409724ba675SRob Herring i2c@9843000 { 410724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 411724ba675SRob Herring reg = <0x9843000 0x110>; 412724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 413724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 414724ba675SRob Herring clock-names = "ssc"; 415724ba675SRob Herring clock-frequency = <400000>; 416724ba675SRob Herring pinctrl-names = "default"; 417724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c3_default>; 418724ba675SRob Herring #address-cells = <1>; 419724ba675SRob Herring #size-cells = <0>; 420724ba675SRob Herring 421724ba675SRob Herring status = "disabled"; 422724ba675SRob Herring }; 423724ba675SRob Herring 424724ba675SRob Herring i2c@9844000 { 425724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 426724ba675SRob Herring reg = <0x9844000 0x110>; 427724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 428724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 429724ba675SRob Herring clock-names = "ssc"; 430724ba675SRob Herring clock-frequency = <400000>; 431724ba675SRob Herring pinctrl-names = "default"; 432724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c4_default>; 433724ba675SRob Herring #address-cells = <1>; 434724ba675SRob Herring #size-cells = <0>; 435724ba675SRob Herring 436724ba675SRob Herring status = "disabled"; 437724ba675SRob Herring }; 438724ba675SRob Herring 439724ba675SRob Herring i2c@9845000 { 440724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 441724ba675SRob Herring reg = <0x9845000 0x110>; 442724ba675SRob Herring interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 443724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 444724ba675SRob Herring clock-names = "ssc"; 445724ba675SRob Herring clock-frequency = <400000>; 446724ba675SRob Herring pinctrl-names = "default"; 447724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c5_default>; 448724ba675SRob Herring #address-cells = <1>; 449724ba675SRob Herring #size-cells = <0>; 450724ba675SRob Herring 451724ba675SRob Herring status = "disabled"; 452724ba675SRob Herring }; 453724ba675SRob Herring 454724ba675SRob Herring 455724ba675SRob Herring /* SSCs on SBC */ 456724ba675SRob Herring i2c@9540000 { 457724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 458724ba675SRob Herring reg = <0x9540000 0x110>; 459724ba675SRob Herring interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 460724ba675SRob Herring clocks = <&clk_sysin>; 461724ba675SRob Herring clock-names = "ssc"; 462724ba675SRob Herring clock-frequency = <400000>; 463724ba675SRob Herring pinctrl-names = "default"; 464724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c10_default>; 465724ba675SRob Herring #address-cells = <1>; 466724ba675SRob Herring #size-cells = <0>; 467724ba675SRob Herring 468724ba675SRob Herring status = "disabled"; 469724ba675SRob Herring }; 470724ba675SRob Herring 471724ba675SRob Herring i2c@9541000 { 472724ba675SRob Herring compatible = "st,comms-ssc4-i2c"; 473724ba675SRob Herring reg = <0x9541000 0x110>; 474724ba675SRob Herring interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 475724ba675SRob Herring clocks = <&clk_sysin>; 476724ba675SRob Herring clock-names = "ssc"; 477724ba675SRob Herring clock-frequency = <400000>; 478724ba675SRob Herring pinctrl-names = "default"; 479724ba675SRob Herring pinctrl-0 = <&pinctrl_i2c11_default>; 480724ba675SRob Herring #address-cells = <1>; 481724ba675SRob Herring #size-cells = <0>; 482724ba675SRob Herring 483724ba675SRob Herring status = "disabled"; 484724ba675SRob Herring }; 485724ba675SRob Herring 486724ba675SRob Herring spi@9840000 { 487724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 488724ba675SRob Herring reg = <0x9840000 0x110>; 489724ba675SRob Herring interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 490724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 491724ba675SRob Herring clock-names = "ssc"; 492724ba675SRob Herring pinctrl-0 = <&pinctrl_spi0_default>; 493724ba675SRob Herring pinctrl-names = "default"; 494724ba675SRob Herring #address-cells = <1>; 495724ba675SRob Herring #size-cells = <0>; 496724ba675SRob Herring 497724ba675SRob Herring status = "disabled"; 498724ba675SRob Herring }; 499724ba675SRob Herring 500724ba675SRob Herring spi@9841000 { 501724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 502724ba675SRob Herring reg = <0x9841000 0x110>; 503724ba675SRob Herring interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 504724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 505724ba675SRob Herring clock-names = "ssc"; 506724ba675SRob Herring pinctrl-names = "default"; 507724ba675SRob Herring pinctrl-0 = <&pinctrl_spi1_default>; 508724ba675SRob Herring #address-cells = <1>; 509724ba675SRob Herring #size-cells = <0>; 510724ba675SRob Herring 511724ba675SRob Herring status = "disabled"; 512724ba675SRob Herring }; 513724ba675SRob Herring 514724ba675SRob Herring spi@9842000 { 515724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 516724ba675SRob Herring reg = <0x9842000 0x110>; 517724ba675SRob Herring interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 518724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 519724ba675SRob Herring clock-names = "ssc"; 520724ba675SRob Herring pinctrl-names = "default"; 521724ba675SRob Herring pinctrl-0 = <&pinctrl_spi2_default>; 522724ba675SRob Herring #address-cells = <1>; 523724ba675SRob Herring #size-cells = <0>; 524724ba675SRob Herring 525724ba675SRob Herring status = "disabled"; 526724ba675SRob Herring }; 527724ba675SRob Herring 528724ba675SRob Herring spi@9843000 { 529724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 530724ba675SRob Herring reg = <0x9843000 0x110>; 531724ba675SRob Herring interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 532724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 533724ba675SRob Herring clock-names = "ssc"; 534724ba675SRob Herring pinctrl-names = "default"; 535724ba675SRob Herring pinctrl-0 = <&pinctrl_spi3_default>; 536724ba675SRob Herring #address-cells = <1>; 537724ba675SRob Herring #size-cells = <0>; 538724ba675SRob Herring 539724ba675SRob Herring status = "disabled"; 540724ba675SRob Herring }; 541724ba675SRob Herring 542724ba675SRob Herring spi@9844000 { 543724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 544724ba675SRob Herring reg = <0x9844000 0x110>; 545724ba675SRob Herring interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 546724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 547724ba675SRob Herring clock-names = "ssc"; 548724ba675SRob Herring pinctrl-names = "default"; 549724ba675SRob Herring pinctrl-0 = <&pinctrl_spi4_default>; 550724ba675SRob Herring #address-cells = <1>; 551724ba675SRob Herring #size-cells = <0>; 552724ba675SRob Herring 553724ba675SRob Herring status = "disabled"; 554724ba675SRob Herring }; 555724ba675SRob Herring 556724ba675SRob Herring /* SBC SSC */ 557724ba675SRob Herring spi@9540000 { 558724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 559724ba675SRob Herring reg = <0x9540000 0x110>; 560724ba675SRob Herring interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 561724ba675SRob Herring clocks = <&clk_sysin>; 562724ba675SRob Herring clock-names = "ssc"; 563724ba675SRob Herring pinctrl-names = "default"; 564724ba675SRob Herring pinctrl-0 = <&pinctrl_spi10_default>; 565724ba675SRob Herring #address-cells = <1>; 566724ba675SRob Herring #size-cells = <0>; 567724ba675SRob Herring 568724ba675SRob Herring status = "disabled"; 569724ba675SRob Herring }; 570724ba675SRob Herring 571724ba675SRob Herring spi@9541000 { 572724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 573724ba675SRob Herring reg = <0x9541000 0x110>; 574724ba675SRob Herring interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 575724ba675SRob Herring clocks = <&clk_sysin>; 576724ba675SRob Herring clock-names = "ssc"; 577724ba675SRob Herring pinctrl-names = "default"; 578724ba675SRob Herring pinctrl-0 = <&pinctrl_spi11_default>; 579724ba675SRob Herring #address-cells = <1>; 580724ba675SRob Herring #size-cells = <0>; 581724ba675SRob Herring 582724ba675SRob Herring status = "disabled"; 583724ba675SRob Herring }; 584724ba675SRob Herring 585724ba675SRob Herring spi@9542000 { 586724ba675SRob Herring compatible = "st,comms-ssc4-spi"; 587724ba675SRob Herring reg = <0x9542000 0x110>; 588724ba675SRob Herring interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 589724ba675SRob Herring clocks = <&clk_sysin>; 590724ba675SRob Herring clock-names = "ssc"; 591724ba675SRob Herring pinctrl-names = "default"; 592724ba675SRob Herring pinctrl-0 = <&pinctrl_spi12_default>; 593724ba675SRob Herring #address-cells = <1>; 594724ba675SRob Herring #size-cells = <0>; 595724ba675SRob Herring 596724ba675SRob Herring status = "disabled"; 597724ba675SRob Herring }; 598724ba675SRob Herring 599724ba675SRob Herring mmc0: sdhci@9060000 { 600724ba675SRob Herring compatible = "st,sdhci-stih407", "st,sdhci"; 601724ba675SRob Herring status = "disabled"; 602724ba675SRob Herring reg = <0x09060000 0x7ff>, <0x9061008 0x20>; 603724ba675SRob Herring reg-names = "mmc", "top-mmc-delay"; 604724ba675SRob Herring interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 605724ba675SRob Herring interrupt-names = "mmcirq"; 606724ba675SRob Herring pinctrl-names = "default"; 607724ba675SRob Herring pinctrl-0 = <&pinctrl_mmc0>; 608724ba675SRob Herring clock-names = "mmc", "icn"; 609724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_MMC_0>, 610724ba675SRob Herring <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 611724ba675SRob Herring bus-width = <8>; 612724ba675SRob Herring }; 613724ba675SRob Herring 614724ba675SRob Herring mmc1: sdhci@9080000 { 615724ba675SRob Herring compatible = "st,sdhci-stih407", "st,sdhci"; 616724ba675SRob Herring status = "disabled"; 617724ba675SRob Herring reg = <0x09080000 0x7ff>; 618724ba675SRob Herring reg-names = "mmc"; 619724ba675SRob Herring interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 620724ba675SRob Herring interrupt-names = "mmcirq"; 621724ba675SRob Herring pinctrl-names = "default"; 622724ba675SRob Herring pinctrl-0 = <&pinctrl_sd1>; 623724ba675SRob Herring clock-names = "mmc", "icn"; 624724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_MMC_1>, 625724ba675SRob Herring <&clk_s_c0_flexgen CLK_RX_ICN_HVA>; 626724ba675SRob Herring resets = <&softreset STIH407_MMC1_SOFTRESET>; 627724ba675SRob Herring bus-width = <4>; 628724ba675SRob Herring }; 629724ba675SRob Herring 630724ba675SRob Herring /* Watchdog and Real-Time Clock */ 631724ba675SRob Herring lpc@8787000 { 632724ba675SRob Herring compatible = "st,stih407-lpc"; 633724ba675SRob Herring reg = <0x8787000 0x1000>; 634724ba675SRob Herring interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; 635724ba675SRob Herring clocks = <&clk_s_d3_flexgen CLK_LPC_0>; 636724ba675SRob Herring timeout-sec = <120>; 637724ba675SRob Herring st,syscfg = <&syscfg_core>; 638724ba675SRob Herring st,lpc-mode = <ST_LPC_MODE_WDT>; 639724ba675SRob Herring }; 640724ba675SRob Herring 641724ba675SRob Herring lpc@8788000 { 642724ba675SRob Herring compatible = "st,stih407-lpc"; 643724ba675SRob Herring reg = <0x8788000 0x1000>; 644724ba675SRob Herring interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; 645724ba675SRob Herring clocks = <&clk_s_d3_flexgen CLK_LPC_1>; 646724ba675SRob Herring st,lpc-mode = <ST_LPC_MODE_CLKSRC>; 647724ba675SRob Herring }; 648724ba675SRob Herring 649724ba675SRob Herring spifsm: spifsm@9022000 { 650724ba675SRob Herring compatible = "st,spi-fsm"; 651724ba675SRob Herring reg = <0x9022000 0x1000>; 652724ba675SRob Herring reg-names = "spi-fsm"; 653724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>; 654724ba675SRob Herring clock-names = "emi_clk"; 655724ba675SRob Herring pinctrl-names = "default"; 656724ba675SRob Herring pinctrl-0 = <&pinctrl_fsm>; 657724ba675SRob Herring st,syscfg = <&syscfg_core>; 658724ba675SRob Herring st,boot-device-reg = <0x8c4>; 659724ba675SRob Herring st,boot-device-spi = <0x68>; 660724ba675SRob Herring 661724ba675SRob Herring status = "disabled"; 662724ba675SRob Herring }; 663724ba675SRob Herring 664724ba675SRob Herring sata0: sata@9b20000 { 665724ba675SRob Herring compatible = "st,ahci"; 666724ba675SRob Herring reg = <0x9b20000 0x1000>; 667724ba675SRob Herring 668724ba675SRob Herring interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 669724ba675SRob Herring interrupt-names = "hostc"; 670724ba675SRob Herring 671724ba675SRob Herring phys = <&phy_port0 PHY_TYPE_SATA>; 672724ba675SRob Herring phy-names = "ahci_phy"; 673724ba675SRob Herring 674724ba675SRob Herring resets = <&powerdown STIH407_SATA0_POWERDOWN>, 675724ba675SRob Herring <&softreset STIH407_SATA0_SOFTRESET>, 676724ba675SRob Herring <&softreset STIH407_SATA0_PWR_SOFTRESET>; 677724ba675SRob Herring reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; 678724ba675SRob Herring 679724ba675SRob Herring clock-names = "ahci_clk"; 680724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 681724ba675SRob Herring 682724ba675SRob Herring ports-implemented = <0x1>; 683724ba675SRob Herring 684724ba675SRob Herring status = "disabled"; 685724ba675SRob Herring }; 686724ba675SRob Herring 687724ba675SRob Herring sata1: sata@9b28000 { 688724ba675SRob Herring compatible = "st,ahci"; 689724ba675SRob Herring reg = <0x9b28000 0x1000>; 690724ba675SRob Herring 691724ba675SRob Herring interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 692724ba675SRob Herring interrupt-names = "hostc"; 693724ba675SRob Herring 694724ba675SRob Herring phys = <&phy_port1 PHY_TYPE_SATA>; 695724ba675SRob Herring phy-names = "ahci_phy"; 696724ba675SRob Herring 697724ba675SRob Herring resets = <&powerdown STIH407_SATA1_POWERDOWN>, 698724ba675SRob Herring <&softreset STIH407_SATA1_SOFTRESET>, 699724ba675SRob Herring <&softreset STIH407_SATA1_PWR_SOFTRESET>; 700724ba675SRob Herring reset-names = "pwr-dwn", 701724ba675SRob Herring "sw-rst", 702724ba675SRob Herring "pwr-rst"; 703724ba675SRob Herring 704724ba675SRob Herring clock-names = "ahci_clk"; 705724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; 706724ba675SRob Herring 707724ba675SRob Herring ports-implemented = <0x1>; 708724ba675SRob Herring 709724ba675SRob Herring status = "disabled"; 710724ba675SRob Herring }; 711724ba675SRob Herring 712724ba675SRob Herring 713724ba675SRob Herring st_dwc3: dwc3@8f94000 { 714724ba675SRob Herring compatible = "st,stih407-dwc3"; 715724ba675SRob Herring reg = <0x08f94000 0x1000>, <0x110 0x4>; 716724ba675SRob Herring reg-names = "reg-glue", "syscfg-reg"; 717724ba675SRob Herring st,syscfg = <&syscfg_core>; 718724ba675SRob Herring resets = <&powerdown STIH407_USB3_POWERDOWN>, 719724ba675SRob Herring <&softreset STIH407_MIPHY2_SOFTRESET>; 720724ba675SRob Herring reset-names = "powerdown", "softreset"; 721724ba675SRob Herring #address-cells = <1>; 722724ba675SRob Herring #size-cells = <1>; 723724ba675SRob Herring pinctrl-names = "default"; 724724ba675SRob Herring pinctrl-0 = <&pinctrl_usb3>; 725724ba675SRob Herring ranges; 726724ba675SRob Herring 727724ba675SRob Herring status = "disabled"; 728724ba675SRob Herring 729724ba675SRob Herring dwc3: usb@9900000 { 730724ba675SRob Herring compatible = "snps,dwc3"; 731724ba675SRob Herring reg = <0x09900000 0x100000>; 732724ba675SRob Herring interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 733724ba675SRob Herring dr_mode = "host"; 734724ba675SRob Herring phy-names = "usb2-phy", "usb3-phy"; 735724ba675SRob Herring phys = <&usb2_picophy0>, 736724ba675SRob Herring <&phy_port2 PHY_TYPE_USB3>; 737724ba675SRob Herring snps,dis_u3_susphy_quirk; 738724ba675SRob Herring }; 739724ba675SRob Herring }; 740724ba675SRob Herring 741724ba675SRob Herring /* COMMS PWM Module */ 742724ba675SRob Herring pwm0: pwm@9810000 { 743724ba675SRob Herring compatible = "st,sti-pwm"; 744724ba675SRob Herring #pwm-cells = <2>; 745724ba675SRob Herring reg = <0x9810000 0x68>; 746724ba675SRob Herring interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 747724ba675SRob Herring pinctrl-names = "default"; 748724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm0_chan0_default>; 749724ba675SRob Herring clock-names = "pwm"; 750724ba675SRob Herring clocks = <&clk_sysin>; 751724ba675SRob Herring st,pwm-num-chan = <1>; 752724ba675SRob Herring 753724ba675SRob Herring status = "disabled"; 754724ba675SRob Herring }; 755724ba675SRob Herring 756724ba675SRob Herring /* SBC PWM Module */ 757724ba675SRob Herring pwm1: pwm@9510000 { 758724ba675SRob Herring compatible = "st,sti-pwm"; 759724ba675SRob Herring #pwm-cells = <2>; 760724ba675SRob Herring reg = <0x9510000 0x68>; 761724ba675SRob Herring interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 762724ba675SRob Herring pinctrl-names = "default"; 763724ba675SRob Herring pinctrl-0 = <&pinctrl_pwm1_chan0_default 764724ba675SRob Herring &pinctrl_pwm1_chan1_default 765724ba675SRob Herring &pinctrl_pwm1_chan2_default 766724ba675SRob Herring &pinctrl_pwm1_chan3_default>; 767724ba675SRob Herring clock-names = "pwm"; 768724ba675SRob Herring clocks = <&clk_sysin>; 769724ba675SRob Herring st,pwm-num-chan = <4>; 770724ba675SRob Herring 771724ba675SRob Herring status = "disabled"; 772724ba675SRob Herring }; 773724ba675SRob Herring 774724ba675SRob Herring rng10: rng@8a89000 { 775724ba675SRob Herring compatible = "st,rng"; 776724ba675SRob Herring reg = <0x08a89000 0x1000>; 777724ba675SRob Herring clocks = <&clk_sysin>; 778724ba675SRob Herring status = "okay"; 779724ba675SRob Herring }; 780724ba675SRob Herring 781724ba675SRob Herring rng11: rng@8a8a000 { 782724ba675SRob Herring compatible = "st,rng"; 783724ba675SRob Herring reg = <0x08a8a000 0x1000>; 784724ba675SRob Herring clocks = <&clk_sysin>; 785724ba675SRob Herring status = "okay"; 786724ba675SRob Herring }; 787724ba675SRob Herring 788724ba675SRob Herring ethernet0: dwmac@9630000 { 789724ba675SRob Herring device_type = "network"; 790724ba675SRob Herring status = "disabled"; 791724ba675SRob Herring compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710"; 792724ba675SRob Herring reg = <0x9630000 0x8000>, <0x80 0x4>; 793724ba675SRob Herring reg-names = "stmmaceth", "sti-ethconf"; 794724ba675SRob Herring 795724ba675SRob Herring st,syscon = <&syscfg_sbc_reg 0x80>; 796724ba675SRob Herring st,gmac_en; 797724ba675SRob Herring resets = <&softreset STIH407_ETH1_SOFTRESET>; 798724ba675SRob Herring reset-names = "stmmaceth"; 799724ba675SRob Herring 800724ba675SRob Herring interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 801724ba675SRob Herring <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 802724ba675SRob Herring interrupt-names = "macirq", "eth_wake_irq"; 803724ba675SRob Herring 804724ba675SRob Herring /* DMA Bus Mode */ 805724ba675SRob Herring snps,pbl = <8>; 806724ba675SRob Herring 807724ba675SRob Herring pinctrl-names = "default"; 808724ba675SRob Herring pinctrl-0 = <&pinctrl_rgmii1>; 809724ba675SRob Herring 810724ba675SRob Herring clock-names = "stmmaceth", "sti-ethclk"; 811724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>, 812724ba675SRob Herring <&clk_s_c0_flexgen CLK_ETH_PHY>; 813724ba675SRob Herring }; 814724ba675SRob Herring 815724ba675SRob Herring mailbox0: mailbox@8f00000 { 816724ba675SRob Herring compatible = "st,stih407-mailbox"; 817724ba675SRob Herring reg = <0x8f00000 0x1000>; 818724ba675SRob Herring interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 819724ba675SRob Herring #mbox-cells = <2>; 820724ba675SRob Herring mbox-name = "a9"; 821724ba675SRob Herring status = "okay"; 822724ba675SRob Herring }; 823724ba675SRob Herring 824724ba675SRob Herring mailbox1: mailbox@8f01000 { 825724ba675SRob Herring compatible = "st,stih407-mailbox"; 826724ba675SRob Herring reg = <0x8f01000 0x1000>; 827724ba675SRob Herring #mbox-cells = <2>; 828724ba675SRob Herring mbox-name = "st231_gp_1"; 829724ba675SRob Herring status = "okay"; 830724ba675SRob Herring }; 831724ba675SRob Herring 832724ba675SRob Herring mailbox2: mailbox@8f02000 { 833724ba675SRob Herring compatible = "st,stih407-mailbox"; 834724ba675SRob Herring reg = <0x8f02000 0x1000>; 835724ba675SRob Herring #mbox-cells = <2>; 836724ba675SRob Herring mbox-name = "st231_gp_0"; 837724ba675SRob Herring status = "okay"; 838724ba675SRob Herring }; 839724ba675SRob Herring 840724ba675SRob Herring mailbox3: mailbox@8f03000 { 841724ba675SRob Herring compatible = "st,stih407-mailbox"; 842724ba675SRob Herring reg = <0x8f03000 0x1000>; 843724ba675SRob Herring #mbox-cells = <2>; 844724ba675SRob Herring mbox-name = "st231_audio_video"; 845724ba675SRob Herring status = "okay"; 846724ba675SRob Herring }; 847724ba675SRob Herring 848724ba675SRob Herring /* fdma audio */ 849724ba675SRob Herring fdma0: dma-controller@8e20000 { 850724ba675SRob Herring compatible = "st,stih407-fdma-mpe31-11", "st,slim-rproc"; 851724ba675SRob Herring reg = <0x8e20000 0x8000>, 852724ba675SRob Herring <0x8e30000 0x3000>, 853724ba675SRob Herring <0x8e37000 0x1000>, 854724ba675SRob Herring <0x8e38000 0x8000>; 855724ba675SRob Herring reg-names = "slimcore", "dmem", "peripherals", "imem"; 856724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FDMA>, 857724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>, 858724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>, 859724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>; 860724ba675SRob Herring interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 861724ba675SRob Herring dma-channels = <16>; 862724ba675SRob Herring #dma-cells = <3>; 863724ba675SRob Herring }; 864724ba675SRob Herring 865724ba675SRob Herring /* fdma app */ 866724ba675SRob Herring fdma1: dma-controller@8e40000 { 867724ba675SRob Herring compatible = "st,stih407-fdma-mpe31-12", "st,slim-rproc"; 868724ba675SRob Herring reg = <0x8e40000 0x8000>, 869724ba675SRob Herring <0x8e50000 0x3000>, 870724ba675SRob Herring <0x8e57000 0x1000>, 871724ba675SRob Herring <0x8e58000 0x8000>; 872724ba675SRob Herring reg-names = "slimcore", "dmem", "peripherals", "imem"; 873724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FDMA>, 874724ba675SRob Herring <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 875724ba675SRob Herring <&clk_s_c0_flexgen CLK_TX_ICN_DMU>, 876724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>; 877724ba675SRob Herring 878724ba675SRob Herring interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 879724ba675SRob Herring dma-channels = <16>; 880724ba675SRob Herring #dma-cells = <3>; 881724ba675SRob Herring 882724ba675SRob Herring status = "disabled"; 883724ba675SRob Herring }; 884724ba675SRob Herring 885724ba675SRob Herring /* fdma free running */ 886724ba675SRob Herring fdma2: dma-controller@8e60000 { 887724ba675SRob Herring compatible = "st,stih407-fdma-mpe31-13", "st,slim-rproc"; 888724ba675SRob Herring reg = <0x8e60000 0x8000>, 889724ba675SRob Herring <0x8e70000 0x3000>, 890724ba675SRob Herring <0x8e77000 0x1000>, 891724ba675SRob Herring <0x8e78000 0x8000>; 892724ba675SRob Herring reg-names = "slimcore", "dmem", "peripherals", "imem"; 893724ba675SRob Herring interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 894724ba675SRob Herring dma-channels = <16>; 895724ba675SRob Herring #dma-cells = <3>; 896724ba675SRob Herring clocks = <&clk_s_c0_flexgen CLK_FDMA>, 897724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>, 898724ba675SRob Herring <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>, 899724ba675SRob Herring <&clk_s_c0_flexgen CLK_EXT2F_A9>; 900724ba675SRob Herring 901724ba675SRob Herring status = "disabled"; 902724ba675SRob Herring }; 903724ba675SRob Herring 904724ba675SRob Herring sti_uni_player0: sti-uni-player@8d80000 { 905724ba675SRob Herring compatible = "st,stih407-uni-player-hdmi"; 906724ba675SRob Herring #sound-dai-cells = <0>; 907724ba675SRob Herring st,syscfg = <&syscfg_core>; 908724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_PCM_0>; 909724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 0>, <&clk_s_d0_flexgen CLK_PCM_0>; 910724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 0>; 911724ba675SRob Herring assigned-clock-rates = <50000000>; 912724ba675SRob Herring reg = <0x8d80000 0x158>; 913724ba675SRob Herring interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 914724ba675SRob Herring dmas = <&fdma0 2 0 1>; 915724ba675SRob Herring dma-names = "tx"; 916724ba675SRob Herring 917724ba675SRob Herring status = "disabled"; 918724ba675SRob Herring }; 919724ba675SRob Herring 920724ba675SRob Herring sti_uni_player1: sti-uni-player@8d81000 { 921724ba675SRob Herring compatible = "st,stih407-uni-player-pcm-out"; 922724ba675SRob Herring #sound-dai-cells = <0>; 923724ba675SRob Herring st,syscfg = <&syscfg_core>; 924724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_PCM_1>; 925724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 1>, <&clk_s_d0_flexgen CLK_PCM_1>; 926724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 1>; 927724ba675SRob Herring assigned-clock-rates = <50000000>; 928724ba675SRob Herring reg = <0x8d81000 0x158>; 929724ba675SRob Herring interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 930724ba675SRob Herring dmas = <&fdma0 3 0 1>; 931724ba675SRob Herring dma-names = "tx"; 932724ba675SRob Herring 933724ba675SRob Herring status = "disabled"; 934724ba675SRob Herring }; 935724ba675SRob Herring 936724ba675SRob Herring sti_uni_player2: sti-uni-player@8d82000 { 937724ba675SRob Herring compatible = "st,stih407-uni-player-dac"; 938724ba675SRob Herring #sound-dai-cells = <0>; 939724ba675SRob Herring st,syscfg = <&syscfg_core>; 940724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_PCM_2>; 941724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 2>, <&clk_s_d0_flexgen CLK_PCM_2>; 942724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 2>; 943724ba675SRob Herring assigned-clock-rates = <50000000>; 944724ba675SRob Herring reg = <0x8d82000 0x158>; 945724ba675SRob Herring interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 946724ba675SRob Herring dmas = <&fdma0 4 0 1>; 947724ba675SRob Herring dma-names = "tx"; 948724ba675SRob Herring 949724ba675SRob Herring status = "disabled"; 950724ba675SRob Herring }; 951724ba675SRob Herring 952724ba675SRob Herring sti_uni_player3: sti-uni-player@8d85000 { 953724ba675SRob Herring compatible = "st,stih407-uni-player-spdif"; 954724ba675SRob Herring #sound-dai-cells = <0>; 955724ba675SRob Herring st,syscfg = <&syscfg_core>; 956724ba675SRob Herring clocks = <&clk_s_d0_flexgen CLK_SPDIFF>; 957724ba675SRob Herring assigned-clocks = <&clk_s_d0_quadfs 3>, <&clk_s_d0_flexgen CLK_SPDIFF>; 958724ba675SRob Herring assigned-clock-parents = <0>, <&clk_s_d0_quadfs 3>; 959724ba675SRob Herring assigned-clock-rates = <50000000>; 960724ba675SRob Herring reg = <0x8d85000 0x158>; 961724ba675SRob Herring interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 962724ba675SRob Herring dmas = <&fdma0 7 0 1>; 963724ba675SRob Herring dma-names = "tx"; 964724ba675SRob Herring 965724ba675SRob Herring status = "disabled"; 966724ba675SRob Herring }; 967724ba675SRob Herring 968724ba675SRob Herring sti_uni_reader0: sti-uni-reader@8d83000 { 969724ba675SRob Herring compatible = "st,stih407-uni-reader-pcm_in"; 970724ba675SRob Herring #sound-dai-cells = <0>; 971724ba675SRob Herring st,syscfg = <&syscfg_core>; 972724ba675SRob Herring reg = <0x8d83000 0x158>; 973724ba675SRob Herring interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 974724ba675SRob Herring dmas = <&fdma0 5 0 1>; 975724ba675SRob Herring dma-names = "rx"; 976724ba675SRob Herring 977724ba675SRob Herring status = "disabled"; 978724ba675SRob Herring }; 979724ba675SRob Herring 980724ba675SRob Herring sti_uni_reader1: sti-uni-reader@8d84000 { 981724ba675SRob Herring compatible = "st,stih407-uni-reader-hdmi"; 982724ba675SRob Herring #sound-dai-cells = <0>; 983724ba675SRob Herring st,syscfg = <&syscfg_core>; 984724ba675SRob Herring reg = <0x8d84000 0x158>; 985724ba675SRob Herring interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 986724ba675SRob Herring dmas = <&fdma0 6 0 1>; 987724ba675SRob Herring dma-names = "rx"; 988724ba675SRob Herring 989724ba675SRob Herring status = "disabled"; 990724ba675SRob Herring }; 991724ba675SRob Herring }; 992724ba675SRob Herring}; 993