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/linux/drivers/net/ethernet/microchip/sparx5/
H A Dsparx5_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
215 bool is_sparx5(struct sparx5 *sparx5) in is_sparx5() argument
217 switch (sparx5->target_ct) { in is_sparx5()
234 static void sparx5_init_features(struct sparx5 *sparx5) in sparx5_init_features() argument
236 switch (sparx5->target_ct) { in sparx5_init_features()
256 sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); in sparx5_init_features()
263 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) in sparx5_has_feature() argument
[all …]
H A Dsparx5_port.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
37 switch (lp_abil & LPA_SGMII_SPD_MASK) { in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
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H A Dsparx5_vcap_debugfs.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver VCAP debugFS implementation
18 switch (value) { in sparx5_vcap_is0_etype_str()
42 switch (value) { in sparx5_vcap_is0_mpls_str()
66 switch (value) { in sparx5_vcap_is0_mlbs_str()
76 static void sparx5_vcap_is0_port_keys(struct sparx5 *sparx5, in sparx5_vcap_is0_port_keys() argument
84 out->prf(out->dst, " port[%02d] (%s): ", port->portno, in sparx5_vcap_is0_port_keys()
85 netdev_name(port->ndev)); in sparx5_vcap_is0_port_keys()
86 for (lookup = 0; lookup < admin->lookups; ++lookup) { in sparx5_vcap_is0_port_keys()
87 out->prf(out->dst, "\n Lookup %d: ", lookup); in sparx5_vcap_is0_port_keys()
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H A Dsparx5_ptp.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
25 static u64 sparx5_ptp_get_1ppm(struct sparx5 *sparx5) in sparx5_ptp_get_1ppm() argument
30 * (1/1000000)/((2^-59)/X) in sparx5_ptp_get_1ppm()
35 switch (sparx5->coreclock) { in sparx5_ptp_get_1ppm()
56 static u64 sparx5_ptp_get_nominal_value(struct sparx5 *sparx5) in sparx5_ptp_get_nominal_value() argument
60 switch (sparx5->coreclock) { in sparx5_ptp_get_nominal_value()
85 struct sparx5 *sparx5 = port->sparx5; in sparx5_ptp_hwtstamp_set() local
[all …]
H A Dsparx5_calendar.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
37 static u32 sparx5_target_bandwidth(struct sparx5 *sparx5) in sparx5_target_bandwidth() argument
39 switch (sparx5->target_ct) { in sparx5_target_bandwidth()
78 switch (cclock) { in sparx5_clk_to_bandwidth()
90 switch (speed) { in sparx5_cal_speed_to_value()
104 switch (bw) { in sparx5_bandwidth_to_calendar()
118 enum sparx5_cal_bw sparx5_get_port_cal_speed(struct sparx5 *sparx5, u32 portno) in sparx5_get_port_cal_speed() argument
122 if (portno >= sparx5->data->consts->n_ports) { in sparx5_get_port_cal_speed()
125 sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0) || in sparx5_get_port_cal_speed()
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H A Dsparx5_tc_matchall.c1 // SPDX-License-Identifier: GPL-2.0+
20 if (entry->cookie == cookie) in sparx5_tc_matchall_entry_find()
33 entry->port = port; in sparx5_tc_matchall_parse_action()
34 entry->type = action->id; in sparx5_tc_matchall_parse_action()
35 entry->ingress = ingress; in sparx5_tc_matchall_parse_action()
36 entry->cookie = cookie; in sparx5_tc_matchall_parse_action()
43 entry->mirror.port = netdev_priv(action->dev); in sparx5_tc_matchall_parse_mirror_action()
53 struct sparx5 *sparx5; in sparx5_tc_matchall_replace() local
56 if (!flow_offload_has_one_action(&tmo->rule->action)) { in sparx5_tc_matchall_replace()
57 NL_SET_ERR_MSG_MOD(tmo->common.extack, in sparx5_tc_matchall_replace()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0-only
3 # Makefile for the Microchip Sparx5 network device drivers.
6 obj-$(CONFIG_SPARX5_SWITCH) += sparx5-switch.o
8 sparx5-switch-y := sparx5_main.o sparx5_packet.o \
16 sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o
17 sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o
19 sparx5-switch-$(CONFIG_LAN969X_SWITCH) += lan969x/lan969x_regs.o \
28 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap
29 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma
H A Dsparx5_mirror.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
24 static u64 sparx5_mirror_port_get(struct sparx5 *sparx5, u32 idx) in sparx5_mirror_port_get() argument
28 val = spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_get()
30 if (is_sparx5(sparx5)) in sparx5_mirror_port_get()
31 val |= (u64)spx5_rd(sparx5, ANA_AC_PROBE_PORT_CFG1(idx)) << 32; in sparx5_mirror_port_get()
37 static void sparx5_mirror_port_add(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_add() argument
45 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG(idx)); in sparx5_mirror_port_add()
47 return spx5_rmw(val, val, sparx5, ANA_AC_PROBE_PORT_CFG1(idx)); in sparx5_mirror_port_add()
51 static void sparx5_mirror_port_del(struct sparx5 *sparx5, u32 idx, u32 portno) in sparx5_mirror_port_del() argument
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H A Dsparx5_ethtool.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
201 static void sparx5_get_queue_sys_stats(struct sparx5 *sparx5, int portno) in sparx5_get_queue_sys_stats() argument
208 portstats = &sparx5->stats[portno * sparx5->num_stats]; in sparx5_get_queue_sys_stats()
209 mutex_lock(&sparx5->queue_stats_lock); in sparx5_get_queue_sys_stats()
210 spx5_wr(XQS_STAT_CFG_STAT_VIEW_SET(portno), sparx5, XQS_STAT_CFG); in sparx5_get_queue_sys_stats()
214 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
218 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
222 sparx5_update_counter(stats, spx5_rd(sparx5, XQS_CNT(addr))); in sparx5_get_queue_sys_stats()
224 spx5_rd(sparx5, XQS_CNT(32))); in sparx5_get_queue_sys_stats()
[all …]
H A Dsparx5_vcap_debugfs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip Sparx5 Switch driver VCAP implementation
H A Dsparx5_tc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip Sparx5 Switch driver
H A Dsparx5_pool.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
12 return --id; in sparx5_pool_id_to_idx()
28 if (e_itr->ref_cnt == 0) in sparx5_pool_put()
29 return -EINVAL; in sparx5_pool_put()
31 return --e_itr->ref_cnt; in sparx5_pool_put()
43 if (e_itr->ref_cnt == 0) { in sparx5_pool_get()
45 return ++e_itr->ref_cnt; in sparx5_pool_get()
49 return -ENOSPC; in sparx5_pool_get()
59 int i, ret = -ENOSPC; in sparx5_pool_get_with_idx()
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/linux/Documentation/devicetree/bindings/arm/
H A Dmicrochip,sparx5.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Boards
10 - Lars Povlsen <lars.povlsen@microchip.com>
13 The Microchip Sparx5 SoC is a ARMv8-based used in a family of
14 gigabit TSN-capable gigabit switches.
16 The SparX-5 Ethernet switch family provides a rich set of switching
17 features such as advanced TCAM-based VLAN and QoS processing
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/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/microchip,sparx5.h>
11 compatible = "microchip,sparx5";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <1>;
23 stdout-path = "serial0:115200n8";
27 #address-cells = <1>;
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/linux/drivers/net/ethernet/microchip/sparx5/lan969x/
H A Dlan969x.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip lan969x Switch driver
123 static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port) in lan969x_get_dev_mode_bit() argument
129 switch (port) { in lan969x_get_dev_mode_bit()
143 static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port) in lan969x_port_dev_mapping() argument
146 switch (port) { in lan969x_port_dev_mapping()
159 switch (port) { in lan969x_port_dev_mapping()
187 static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port, in lan969x_port_mux_set() argument
190 u32 portno = port->portno; in lan969x_port_mux_set()
193 if (port->conf.portmode == conf->portmode) in lan969x_port_mux_set()
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H A Dlan969x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Microchip lan969x Switch driver
10 #include "../sparx5/sparx5_main.h"
11 #include "../sparx5/sparx5_regs.h"
12 #include "../sparx5/sparx5_vcap_impl.h"
68 int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
76 int lan969x_fdma_init(struct sparx5 *sparx5);
77 int lan969x_fdma_deinit(struct sparx5 *sparx5);
79 int lan969x_fdma_xmit(struct sparx5 *sparx5, u32 *ifh, struct sk_buff *skb,
H A Dlan969x_calendar.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip lan969x Switch driver
49 return -EINVAL; in lan969x_dsm_cal_idx_get()
58 return -ENOENT; in lan969x_dsm_cal_idx_get()
77 int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi, in lan969x_dsm_calendar_calc() argument
86 taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock); in lan969x_dsm_calendar_calc()
88 memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi], in lan969x_dsm_calendar_calc()
92 u32 portno = data->taxi_ports[i]; in lan969x_dsm_calendar_calc()
95 bw = sparx5_get_port_cal_speed(sparx5, portno); in lan969x_dsm_calendar_calc()
97 if (portno < sparx5->data->consts->n_ports_all) in lan969x_dsm_calendar_calc()
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/linux/Documentation/devicetree/bindings/reset/
H A Dmicrochip,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Sparx5 Switch Reset Controller
10 - Steen Hegelund <steen.hegelund@microchip.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
14 The Microchip Sparx5 Switch provides reset control and implements the following
16 - One Time Switch Core Reset (Soft Reset)
20 pattern: "^reset-controller@[0-9a-f]+$"
24 - microchip,sparx5-switch-reset
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/linux/drivers/reset/
H A Dreset-microchip-sparx5.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch Reset driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
16 #include <linux/reset-controller.h>
43 regmap_update_bits(ctx->cpu_ctrl, ctx->props->protect_reg, in sparx5_switch_reset()
44 ctx->props->protect_bit, ctx->props->protect_bit); in sparx5_switch_reset()
47 regmap_write(ctx->gcb_ctrl, ctx->props->reset_reg, in sparx5_switch_reset()
48 ctx->props->reset_bit); in sparx5_switch_reset()
51 return regmap_read_poll_timeout(ctx->gcb_ctrl, ctx->props->reset_reg, val, in sparx5_switch_reset()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
87 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
90 If compiled as module, it will be called reset-gpio.
132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
149 tristate "Microchip Sparx5 reset driver"
154 This driver supports switch core reset for the Microchip Sparx5 SoC.
208 Raspberry Pi 4's co-processor controls some of the board's HW
211 interfacing with RPi4's co-processor and model these firmware
242 - Altera SoCFPGAs
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/linux/drivers/hwmon/
H A Dsparx5-temp.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* Sparx5 SoC temperature sensor driver
31 u32 val = readl(hwmon->base + TEMP_CFG); in s5_temp_enable()
32 u32 clk = clk_get_rate(hwmon->clk) / USEC_PER_SEC; in s5_temp_enable()
38 writel(val, hwmon->base + TEMP_CFG); in s5_temp_enable()
48 switch (attr) { in s5_read()
50 stat = readl_relaxed(hwmon->base + TEMP_STAT); in s5_read()
52 return -EAGAIN; in s5_read()
56 * Temp(C) = TEMP_SENSOR_STAT.TEMP / 4096 * 352.2 - 109.4 in s5_read()
58 value = DIV_ROUND_CLOSEST(value * 3522, 4096) - 1094; in s5_read()
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/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmicrochip,sparx5-sgpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/microchip,sparx5-sgpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lars Povlsen <lars.povlsen@microchip.com>
21 pattern: "^gpio@[0-9a-f]+$"
25 - microchip,sparx5-sgpio
26 - mscc,ocelot-sgpio
27 - mscc,luton-sgpio
29 "#address-cells":
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H A Dmscc,ocelot-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mscc,ocelot-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
11 - Lars Povlsen <lars.povlsen@microchip.com>
16 - enum:
17 - microchip,lan966x-pinctrl
18 - microchip,lan9691-pinctrl
19 - microchip,sparx5-pinctrl
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/linux/Documentation/devicetree/bindings/mfd/
H A Dmscc,ocelot.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
13 The Ocelot ethernet switch family contains chips that have an internal CPU
18 The switch family is a multi-port networking switch that supports many
25 - mscc,vsc7512
30 "#address-cells":
33 "#size-cells":
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/linux/arch/arm/boot/dts/microchip/
H A Dlan966x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/mfd/atmel-flexcom.h>
14 #include <dt-bindings/dma/at91.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/clock/microchip,lan966x.h>
21 interrupt-parent = <&gic>;
22 #address-cells = <1>;
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