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/linux/drivers/pinctrl/intel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
8 select PINCTRL_INTEL
11 platforms. Supports 3 banks with 102, 28 and 44 gpios.
19 select PINCTRL_INTEL
22 allows configuring of SoC pins and using them as GPIOs.
26 select PINCTRL_INTEL
30 using them as GPIOs.
34 select PINMUX
35 select PINCONF
36 select GENERIC_PINCONF
[all …]
H A DKconfig.tng1 # SPDX-License-Identifier: GPL-2.0-only
8 select PINMUX
9 select PINCONF
10 select GENERIC_PINCONF
15 If built as a module its name will be pinctrl-tangier.
19 select PINCTRL_TANGIER
21 Intel Merrifield Family-Level Interface Shim (FLIS) driver provides
23 GPIOs.
27 select PINCTRL_TANGIER
29 Intel Moorefield Family-Level Interface Shim (FLIS) driver provides
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/linux/drivers/gpio/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
18 int "Maximum number of GPIOs for fast path"
39 select IRQ_DOMAIN
46 from PowerPC. Existing drivers using this interface need to select
47 this symbol, but new drivers should use the generic gpio-regmap
55 These checks help ensure that GPIOs have been properly initialized
57 non-sleeping contexts. They can make bitbanged serial protocols
64 select GPIO_CDEV # We need to encourage the new ABI
66 Say Y here to add the legacy sysfs interface for GPIOs.
77 for GPIOs. The character device allows userspace to control GPIOs
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/linux/Documentation/devicetree/bindings/usb/
H A Dgpio-sbu-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/usb/gpio-sbu-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based SBU mux
10 - Bjorn Andersson <andersson@kernel.org>
13 In USB Type-C applications the SBU lines needs to be connected, disconnected
21 - enum:
22 - nxp,cbdtu02043
23 - onnn,fsusb43l10x
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/linux/Documentation/devicetree/bindings/spi/
H A Dfsl-spi.txt4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
19 The gpios will be referred to as reg = <index> in the SPI child nodes.
20 If unspecified, a single SPI device without a chip select can be used.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
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H A Dspi-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
23 sck-gpios:
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/linux/Documentation/devicetree/bindings/sound/
H A Dasahi-kasei,ak4458.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/sound/asahi-kasei,ak4458.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 - asahi-kasei,ak4458
16 - asahi-kasei,ak4497
21 avdd-supply:
24 dvdd-supply:
27 reset-gpios:
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/linux/Documentation/devicetree/bindings/clock/
H A Dgpio-mux-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/gpio-mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergej Sawazki <ce3a@gmx.de>
14 const: gpio-mux-clock
18 - description: First parent clock
19 - description: Second parent clock
21 '#clock-cells':
24 select-gpios:
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/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-lenovo-ix4-300d.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree file for Lenovo Iomega ix4-300d
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "armada-xp-mv78230.dtsi"
15 model = "Lenovo Iomega ix4-300d";
16 compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230",
17 "marvell,armadaxp", "marvell,armada-370-xp";
20 stdout-path = "serial0:115200n8";
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H A Dkirkwood-openrd.dtsi1 // SPDX-License-Identifier: GPL-2.0
12 #include "kirkwood-6281.dtsi"
22 stdout-path = &uart0;
26 pinctrl: pin-controller@10000 {
27 pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>;
28 pinctrl-names = "default";
30 pmx_select28: pmx-select-rs232-rs485 {
34 pmx_sdio_cd: pmx-sdio-cd {
38 pmx_select34: pmx-select-uart-sd {
49 nr-ports = <2>;
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/linux/arch/arm64/boot/dts/marvell/
H A Dcn9130-cf-base.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
9 /dts-v1/;
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
15 #include "cn9130-sr-som.dtsi"
16 #include "cn9130-cf.dtsi"
20 compatible = "solidrun,cn9130-clearfog-base",
21 "solidrun,cn9130-sr-som", "marvell,cn9130";
23 gpio-keys {
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/linux/drivers/pinctrl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
19 select PINMUX
26 select PINCONF
38 select GPIOLIB
39 select GPIOLIB_IRQCHIP
40 select PINMUX
41 select PINCONF
42 select GENERIC_PINCONF
55 select PINMUX
56 select GPIOLIB
[all …]
/linux/Documentation/devicetree/bindings/iio/resolver/
H A Dadi,ad2s1210.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices AD2S1210 Resolver-to-Digital Converter
10 - Michael Hennerich <michael.hennerich@analog.com>
13 The AD2S1210 is a complete 10-bit to 16-bit resolution tracking
14 resolver-to-digital converter, integrating an on-board programmable
29 0 0 Normal mode - position output
30 0 1 Normal mode - velocity output
44 Note on SPI connections: The CS line on the AD2S1210 should hard-wired to
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/linux/Documentation/devicetree/bindings/mtd/
H A Dfsl-upm-nand.txt4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
[all …]
H A Dnand-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
21 pattern: "^nand-controller(@.*)?"
23 "#address-cells":
26 "#size-cells":
31 cs-gpios:
[all …]
/linux/drivers/reset/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
72 select AUXILIARY_BUS
87 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
90 If compiled as module, it will be called reset-gpio.
104 select MFD_SYSCON
111 select AUXILIARY_BUS
120 select REGMAP_MMIO
129 select MFD_SYSCON
132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
[all …]
/linux/Documentation/devicetree/bindings/misc/
H A Difm-csi.txt4 - compatible: "ifm,o2d-csi"
5 - reg: specifies sensor chip select number and associated address range
6 - interrupts: external interrupt line number and interrupt sense mode
8 - gpios: three gpio-specifiers for "capture", "reset" and "master enable"
9 GPIOs (strictly in this order).
10 - ifm,csi-clk-handle: the phandle to a node in the DT describing the sensor
12 - ifm,csi-addr-bus-width: address bus width (valid values are 16, 24, 25)
13 - ifm,csi-data-bus-width: data bus width (valid values are 8 and 16)
14 - ifm,csi-wait-cycles: sensor bus wait cycles
17 - ifm,csi-byte-swap: if this property is present, the byte swapping on
[all …]
/linux/Documentation/devicetree/bindings/eeprom/
H A Dmicrochip,93lc46b.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cory Tusar <cory.tusar@pid1solutions.com>
15 - atmel,at93c46
16 - atmel,at93c46d
17 - atmel,at93c56
18 - atmel,at93c66
19 - eeprom-93xx46
20 - microchip,93lc46b
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-consumer-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-consumer-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <brgl@bgdev.pl>
11 - Linus Walleij <linus.walleij@linaro.org>
14 Pay attention to using proper GPIO flag (e.g. GPIO_ACTIVE_LOW) for the GPIOs
17 select: true
20 enable-gpios:
25 reset-gpios:
[all …]
H A Dspear_spics.txt10 Chipselects can be controlled by software by turning them as GPIOs. SPEAr
17 * compatible: should be defined as "st,spear-spics-gpio"
19 * st-spics,peripcfg-reg: peripheral configuration register offset
20 * st-spics,sw-enable-bit: bit offset to enable sw control
21 * st-spics,cs-value-bit: bit offset to drive chipselect low or high
22 * st-spics,cs-enable-mask: chip select number bit mask
23 * st-spics,cs-enable-shift: chip select number program offset
24 * gpio-controller: Marks the device node as gpio controller
25 * #gpio-cells: should be 1 and will mention chip select number
30 -------
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H A Dgpio-max3191x.txt4 - compatible: Must be one of:
11 - reg: Chip select number.
12 - gpio-controller: Marks the device node as a GPIO controller.
13 - #gpio-cells: Should be two. For consumer use see gpio.txt.
16 - #daisy-chained-devices:
17 Number of chips in the daisy-chain (default is 1).
18 - maxim,modesel-gpios: GPIO pins to configure modesel of each chip.
19 The number of GPIOs must equal "#daisy-chained-devices"
22 - maxim,fault-gpios: GPIO pins to read fault of each chip.
23 The number of GPIOs must equal "#daisy-chained-devices"
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rt6245-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rt6245-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
13 The RT6245 is a high-performance, synchronous step-down converter
18 - $ref: regulator.yaml#
23 - richtek,rt6245
28 enable-gpios:
31 it will be treat as a default-on power.
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-harma.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/i2c/i2c.h>
11 compatible = "facebook,harma-bmc", "aspeed,ast2600";
32 stdout-path = &uart5;
40 iio-hwmon {
41 compatible = "iio-hwmon";
42 io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>,
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/linux/Documentation/userspace-api/gpio/
H A Dsysfs.rst6 been moved to Documentation/ABI/obsolete/sysfs-gpio.
16 ----------------------
18 configure a sysfs user interface to GPIOs. This is different from the
27 then changing its output state, then updating the code before re-enabling
38 Please read Documentation/driver-api/gpio/drivers-on-gpio.rst
44 --------------
47 - Control interfaces used to get userspace control over GPIOs;
49 - GPIOs themselves; and
51 - GPIO controllers ("gpio_chip" instances).
55 The control interfaces are write-only:
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/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = &uart0;
32 compatible = "gpio-keys";
34 button-wps {
[all …]

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