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/linux/drivers/clk/imx/
H A Dclk-imx35.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk.h>
15 #include "clk.h"
33 unsigned char arm, ahb, sel; member
37 { .arm = 1, .ahb = 4, .sel = 0},
38 { .arm = 1, .ahb = 3, .sel = 1},
39 { .arm = 2, .ahb = 2, .sel = 0},
40 { .arm = 0, .ahb = 0, .sel = 0},
41 { .arm = 0, .ahb = 0, .sel = 0},
42 { .arm = 0, .ahb = 0, .sel = 0},
[all …]
H A Dclk-imx6q.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
10 #include <linux/clk.h>
12 #include <linux/clk-provider.h>
15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
20 #include <dt-bindings/clock/imx6qdl-clock.h>
22 #include "clk.h"
154 return -ENOENT; in ldb_di_sel_by_clock_id()
165 return -ENOENT; in ldb_di_sel_by_clock_id()
175 int parent, child, sel; in of_assigned_ldb_sels() local
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-tqmlx2160a-mblx2160a.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 /dts-v1/;
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/net/ti-dp83867.h>
14 #include "fsl-lx2160a-tqmlx2160a.dtsi"
18 compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a",
31 stdout-path = &uart0;
[all …]
/linux/drivers/clk/qcom/
H A Dclk-krait.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/clk-provider.h>
13 #include <asm/krait-l2-accessors.h>
15 #include "clk-krait.h"
23 static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) in __krait_mux_set_sel() argument
30 regval = krait_get_l2_indirect_reg(mux->offset); in __krait_mux_set_sel()
33 if (mux->disable_sec_src_gating) { in __krait_mux_set_sel()
35 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel()
38 regval &= ~(mux->mask << mux->shift); in __krait_mux_set_sel()
39 regval |= (sel & mux->mask) << mux->shift; in __krait_mux_set_sel()
[all …]
/linux/drivers/clk/tegra/
H A Dclk-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
13 #include "clk.h"
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-gpio.c1 // SPDX-License-Identifier: GPL-2.0
3 // mt8186-afe-gpio.c -- Mediatek 8186 afe gpio ctrl
10 #include "mt8186-afe-common.h"
11 #include "mt8186-afe-gpio.h"
112 return -EINVAL; in mt8186_afe_gpio_select()
118 return -EIO; in mt8186_afe_gpio_select()
139 dev_dbg(dev, "%s(), MOSI CLK ON select fail!\n", __func__); in mt8186_afe_gpio_adda_dl()
157 dev_dbg(dev, "%s(), MOSI CLK ON select fail!\n", __func__); in mt8186_afe_gpio_adda_dl()
172 dev_dbg(dev, "%s(), MISO CLK ON select fail!\n", __func__); in mt8186_afe_gpio_adda_ul()
190 dev_dbg(dev, "%s(), MISO CLK OFF select fail!\n", __func__); in mt8186_afe_gpio_adda_ul()
[all …]
/linux/sound/soc/renesas/rcar/
H A Dadg.c1 // SPDX-License-Identifier: GPL-2.0
3 // Helper routines for R-Car sound ADG.
6 #include <linux/clk-provider.h>
34 struct clk *adg;
35 struct clk *clkin[CLKINMAX];
36 struct clk *clkout[CLKOUTMAX];
37 struct clk *null_clk;
52 (i < adg->clkin_size) && \
53 ((pos) = adg->clkin[i]); \
57 (i < adg->clkout_size) && \
[all …]
/linux/include/linux/mfd/
H A Dimx25-tsadc.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 struct clk;
11 struct clk *clk; member
54 _MX25_ADCQ_ITEM((item) - 8, (x)) : _MX25_ADCQ_ITEM((item), (x)))
103 /* ADCQ_CFG (TICR, TCC0-7,GCC0-7) */
107 #define MX25_ADCQ_CFG_NOS(x) (((x) - 1) << 16)
118 #define MX25_ADCQ_CFG_REFP(sel) ((sel) << 7) argument
124 #define MX25_ADCQ_CFG_IN(sel) ((sel) << 4) argument
133 #define MX25_ADCQ_CFG_REFN(sel) ((sel) << 2) argument
/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Dphy_shim.c18 * This is "two-way" interface, acting as the SHIM layer between driver
20 * to do some preprocessing, then reach PHY. On the PHY->driver direction,
35 struct brcms_info *wl; /* pointer to os-specific private state */
47 physhim->wlc_hw = wlc_hw; in wlc_phy_shim_attach()
48 physhim->wlc = wlc; in wlc_phy_shim_attach()
49 physhim->wl = wl; in wlc_phy_shim_attach()
64 brcms_init_timer(physhim->wl, fn, arg, name); in wlapi_init_timer()
85 brcms_intrson(physhim->wl); in wlapi_intrson()
90 return brcms_intrsoff(physhim->wl); in wlapi_intrsoff()
95 brcms_intrsrestore(physhim->wl, macintmask); in wlapi_intrsrestore()
[all …]
/linux/drivers/regulator/
H A Dti-abb-regulator.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * Copyright (C) 2012-2013 Texas Instruments, Inc.
12 #include <linux/clk.h>
26 * FAST_OPP: sets ABB LDO to Forward Body-Bias
27 * SLOW_OPP: sets ABB LDO to Reverse Body-Bias
34 * struct ti_abb_info - ABB information per voltage setting
47 * struct ti_abb_reg - Register description for ABB block
50 * @sr2_wtcnt_value_mask: setup register- sr2_wtcnt_value mask
51 * @fbb_sel_mask: setup register- FBB sel mask
52 * @rbb_sel_mask: setup register- RBB sel mask
[all …]
H A Dstm32-vrefbuf.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk.h>
32 struct clk *clk; member
47 ret = pm_runtime_resume_and_get(priv->dev); in stm32_vrefbuf_enable()
51 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
61 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable()
64 dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n"); in stm32_vrefbuf_enable()
65 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
67 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable()
[all …]
/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-cbus-gpio.txt1 Device tree bindings for i2c-cbus-gpio driver
4 - compatible = "i2c-cbus-gpio";
5 - gpios: clk, dat, sel
6 - #address-cells = <1>;
7 - #size-cells = <0>;
10 - child nodes conforming to i2c bus binding
15 compatible = "i2c-cbus-gpio";
16 gpios = <&gpio 66 0 /* clk */
18 &gpio 64 0 /* sel */
20 #address-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dmediatek,spi-mt65xx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/mediatek,spi-mt65xx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Leilk Liu <leilk.liu@mediatek.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - items:
19 - enum:
20 - mediatek,mt7629-spi
21 - mediatek,mt8365-spi
[all …]
/linux/drivers/media/i2c/
H A Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
18 #include <linux/clk.h>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
147 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
148 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
150 /* 0 : free-run output mode */
[all …]
/linux/drivers/clk/renesas/
H A Drcar-usb2-clock-sel.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas R-Car USB2.0 clock selector
7 * Based on renesas-cpg-mssr.c
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
31 { .id = "hs-usb-if", },
46 u16 val = readw(priv->base + USB20_CLKSET0); in usb2_clock_sel_enable_extal_only()
49 priv->extal, priv->xtal, val); in usb2_clock_sel_enable_extal_only()
51 if (priv->extal && !priv->xtal && val != CLKSET0_EXTAL_ONLY) in usb2_clock_sel_enable_extal_only()
52 writew(CLKSET0_EXTAL_ONLY, priv->base + USB20_CLKSET0); in usb2_clock_sel_enable_extal_only()
[all …]
/linux/sound/soc/meson/
H A Daiu.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk.h>
13 #include <sound/soc-dai.h>
15 #include <dt-bindings/sound/meson-aiu.h>
17 #include "aiu-fifo.h"
33 SND_SOC_DAPM_MUX("SPDIF SRC SEL", SND_SOC_NOPM, 0, 0,
39 { "SPDIF SRC SEL", "SPDIF", "SPDIF FIFO Playback" },
40 { "SPDIF SRC SEL", "I2S", "I2S FIFO Playback" },
41 { "SPDIF Encoder Playback", NULL, "SPDIF SRC SEL" },
52 if (args->args_count != 2) in aiu_of_xlate_dai_name()
[all …]
H A Daxg-spdifout.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <linux/clk.h>
11 #include <sound/soc-dai.h>
19 * applied when the related sel bits are cleared
61 struct clk *mclk;
62 struct clk *pclk;
97 axg_spdifout_enable(priv->map); in axg_spdifout_trigger()
103 axg_spdifout_disable(priv->map); in axg_spdifout_trigger()
107 return -EINVAL; in axg_spdifout_trigger()
116 regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET, in axg_spdifout_mute()
[all …]
H A Daxg-toddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #include <linux/clk.h>
15 #include <sound/soc-dai.h>
17 #include "axg-fifo.h"
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
47 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_toddr_dai_prepare()
65 type = 2; /* 4 samples of 16 bits - right justified */ in axg_toddr_dai_hw_params()
68 type = 4; /* 2 samples of 32 bits - right justified */ in axg_toddr_dai_hw_params()
71 return -EINVAL; in axg_toddr_dai_hw_params()
[all …]
H A Daxg-frddr.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
11 #include <linux/clk.h>
17 #include <sound/soc-dai.h>
19 #include "axg-fifo.h"
41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare()
61 depth = min(period, fifo->depth); in axg_frddr_dai_hw_params()
62 val = (depth / AXG_FIFO_BURST) - 1; in axg_frddr_dai_hw_params()
63 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH, in axg_frddr_dai_hw_params()
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dstm32-dwmac.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/stm32-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Alexandre Torgue <alexandre.torgue@foss.st.com>
12 - Christophe Roullier <christophe.roullier@foss.st.com>
23 - st,stm32-dwmac
24 - st,stm32mp1-dwmac
25 - st,stm32mp13-dwmac
26 - st,stm32mp25-dwmac
[all …]
H A Dti,dp83869.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX
[all …]
/linux/drivers/clk/bcm/
H A Dclk-bcm21664.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
8 #include "dt-bindings/clock/bcm21664.h"
38 .sel = SELECTOR(0x0a10, 0, 2),
64 .sel = SELECTOR(0x0a28, 0, 3),
76 .sel = SELECTOR(0x0a2c, 0, 3),
88 .sel = SELECTOR(0x0a34, 0, 3),
100 .sel = SELECTOR(0x0a30, 0, 3),
159 .sel = SELECTOR(0x0a10, 0, 2),
169 .sel = SELECTOR(0x0a14, 0, 2),
[all …]
H A Dclk-bcm281xx.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
8 #include "dt-bindings/clock/bcm281xx.h"
38 .sel = SELECTOR(0x0a10, 0, 2),
47 .sel = SELECTOR(0x0a04, 0, 2),
55 .sel = SELECTOR(0x0a00, 0, 2),
79 .sel = SELECTOR(0x0e74, 0, 2),
101 .sel = SELECTOR(0x0a28, 0, 3),
113 .sel = SELECTOR(0x0a2c, 0, 3),
125 .sel = SELECTOR(0x0a34, 0, 3),
[all …]
/linux/drivers/clk/sunxi-ng/
H A Dccu_frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
16 if (!(common->features & CCU_FEATURE_FRACTIONAL)) in ccu_frac_helper_is_enabled()
19 return !(readl(common->base + common->reg) & cf->enable); in ccu_frac_helper_is_enabled()
29 if (!(common->features & CCU_FEATURE_FRACTIONAL)) in ccu_frac_helper_enable()
32 spin_lock_irqsave(common->lock, flags); in ccu_frac_helper_enable()
33 reg = readl(common->base + common->reg); in ccu_frac_helper_enable()
34 writel(reg & ~cf->enable, common->base + common->reg); in ccu_frac_helper_enable()
35 spin_unlock_irqrestore(common->lock, flags); in ccu_frac_helper_enable()
[all …]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-afe-clk.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition
100 int mt8195_afe_get_mclk_source_clk_id(int sel);
104 int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk);
105 void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk);
106 int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk);
107 void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk);
108 int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
109 void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk);
110 int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk,
[all …]

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