16746cc85STrevor Wu /* SPDX-License-Identifier: GPL-2.0 */ 26746cc85STrevor Wu /* 36746cc85STrevor Wu * mt8195-afe-clk.h -- Mediatek 8195 afe clock ctrl definition 46746cc85STrevor Wu * 56746cc85STrevor Wu * Copyright (c) 2021 MediaTek Inc. 66746cc85STrevor Wu * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 76746cc85STrevor Wu * Trevor Wu <trevor.wu@mediatek.com> 86746cc85STrevor Wu */ 96746cc85STrevor Wu 106746cc85STrevor Wu #ifndef _MT8195_AFE_CLK_H_ 116746cc85STrevor Wu #define _MT8195_AFE_CLK_H_ 126746cc85STrevor Wu 136746cc85STrevor Wu enum { 146746cc85STrevor Wu /* xtal */ 156746cc85STrevor Wu MT8195_CLK_XTAL_26M, 166746cc85STrevor Wu /* divider */ 176746cc85STrevor Wu MT8195_CLK_TOP_APLL1, 186746cc85STrevor Wu MT8195_CLK_TOP_APLL2, 196746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV0, 206746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV1, 216746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV2, 226746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV3, 236746cc85STrevor Wu MT8195_CLK_TOP_APLL12_DIV9, 246746cc85STrevor Wu /* mux */ 256746cc85STrevor Wu MT8195_CLK_TOP_A1SYS_HP_SEL, 266746cc85STrevor Wu MT8195_CLK_TOP_AUD_INTBUS_SEL, 276746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_H_SEL, 286746cc85STrevor Wu MT8195_CLK_TOP_AUDIO_LOCAL_BUS_SEL, 296746cc85STrevor Wu MT8195_CLK_TOP_DPTX_M_SEL, 306746cc85STrevor Wu MT8195_CLK_TOP_I2SO1_M_SEL, 316746cc85STrevor Wu MT8195_CLK_TOP_I2SO2_M_SEL, 326746cc85STrevor Wu MT8195_CLK_TOP_I2SI1_M_SEL, 336746cc85STrevor Wu MT8195_CLK_TOP_I2SI2_M_SEL, 346746cc85STrevor Wu /* clock gate */ 356746cc85STrevor Wu MT8195_CLK_INFRA_AO_AUDIO_26M_B, 366746cc85STrevor Wu MT8195_CLK_SCP_ADSP_AUDIODSP, 376746cc85STrevor Wu MT8195_CLK_AUD_AFE, 38*ff5a9017STrevor Wu MT8195_CLK_AUD_APLL1_TUNER, 39*ff5a9017STrevor Wu MT8195_CLK_AUD_APLL2_TUNER, 406746cc85STrevor Wu MT8195_CLK_AUD_APLL, 416746cc85STrevor Wu MT8195_CLK_AUD_APLL2, 426746cc85STrevor Wu MT8195_CLK_AUD_DAC, 436746cc85STrevor Wu MT8195_CLK_AUD_ADC, 446746cc85STrevor Wu MT8195_CLK_AUD_DAC_HIRES, 456746cc85STrevor Wu MT8195_CLK_AUD_A1SYS_HP, 466746cc85STrevor Wu MT8195_CLK_AUD_ADC_HIRES, 476746cc85STrevor Wu MT8195_CLK_AUD_ADDA6_ADC, 486746cc85STrevor Wu MT8195_CLK_AUD_ADDA6_ADC_HIRES, 496746cc85STrevor Wu MT8195_CLK_AUD_I2SIN, 506746cc85STrevor Wu MT8195_CLK_AUD_TDM_IN, 516746cc85STrevor Wu MT8195_CLK_AUD_I2S_OUT, 526746cc85STrevor Wu MT8195_CLK_AUD_TDM_OUT, 536746cc85STrevor Wu MT8195_CLK_AUD_HDMI_OUT, 546746cc85STrevor Wu MT8195_CLK_AUD_ASRC11, 556746cc85STrevor Wu MT8195_CLK_AUD_ASRC12, 566746cc85STrevor Wu MT8195_CLK_AUD_A1SYS, 576746cc85STrevor Wu MT8195_CLK_AUD_A2SYS, 586746cc85STrevor Wu MT8195_CLK_AUD_PCMIF, 596746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL1, 606746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL2, 616746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL3, 626746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL4, 636746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL5, 646746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL6, 656746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL8, 666746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL9, 676746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_UL10, 686746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL2, 696746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL3, 706746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL6, 716746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL7, 726746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL8, 736746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL10, 746746cc85STrevor Wu MT8195_CLK_AUD_MEMIF_DL11, 756746cc85STrevor Wu MT8195_CLK_NUM, 766746cc85STrevor Wu }; 776746cc85STrevor Wu 786746cc85STrevor Wu enum { 796746cc85STrevor Wu MT8195_MCK_SEL_26M, 806746cc85STrevor Wu MT8195_MCK_SEL_APLL1, 816746cc85STrevor Wu MT8195_MCK_SEL_APLL2, 826746cc85STrevor Wu MT8195_MCK_SEL_APLL3, 836746cc85STrevor Wu MT8195_MCK_SEL_APLL4, 846746cc85STrevor Wu MT8195_MCK_SEL_APLL5, 856746cc85STrevor Wu MT8195_MCK_SEL_HDMIRX_APLL, 866746cc85STrevor Wu MT8195_MCK_SEL_NUM, 876746cc85STrevor Wu }; 886746cc85STrevor Wu 89*ff5a9017STrevor Wu enum { 90*ff5a9017STrevor Wu MT8195_AUD_PLL1, 91*ff5a9017STrevor Wu MT8195_AUD_PLL2, 92*ff5a9017STrevor Wu MT8195_AUD_PLL3, 93*ff5a9017STrevor Wu MT8195_AUD_PLL4, 94*ff5a9017STrevor Wu MT8195_AUD_PLL5, 95*ff5a9017STrevor Wu MT8195_AUD_PLL_NUM, 96*ff5a9017STrevor Wu }; 97*ff5a9017STrevor Wu 986746cc85STrevor Wu struct mtk_base_afe; 996746cc85STrevor Wu 1006746cc85STrevor Wu int mt8195_afe_get_mclk_source_clk_id(int sel); 1016746cc85STrevor Wu int mt8195_afe_get_mclk_source_rate(struct mtk_base_afe *afe, int apll); 1026746cc85STrevor Wu int mt8195_afe_get_default_mclk_source_by_rate(int rate); 1036746cc85STrevor Wu int mt8195_afe_init_clock(struct mtk_base_afe *afe); 1046746cc85STrevor Wu int mt8195_afe_enable_clk(struct mtk_base_afe *afe, struct clk *clk); 1056746cc85STrevor Wu void mt8195_afe_disable_clk(struct mtk_base_afe *afe, struct clk *clk); 1066746cc85STrevor Wu int mt8195_afe_prepare_clk(struct mtk_base_afe *afe, struct clk *clk); 1076746cc85STrevor Wu void mt8195_afe_unprepare_clk(struct mtk_base_afe *afe, struct clk *clk); 1086746cc85STrevor Wu int mt8195_afe_enable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk); 1096746cc85STrevor Wu void mt8195_afe_disable_clk_atomic(struct mtk_base_afe *afe, struct clk *clk); 1106746cc85STrevor Wu int mt8195_afe_set_clk_rate(struct mtk_base_afe *afe, struct clk *clk, 1116746cc85STrevor Wu unsigned int rate); 1126746cc85STrevor Wu int mt8195_afe_set_clk_parent(struct mtk_base_afe *afe, struct clk *clk, 1136746cc85STrevor Wu struct clk *parent); 1146746cc85STrevor Wu int mt8195_afe_enable_main_clock(struct mtk_base_afe *afe); 1156746cc85STrevor Wu int mt8195_afe_disable_main_clock(struct mtk_base_afe *afe); 1166746cc85STrevor Wu int mt8195_afe_enable_reg_rw_clk(struct mtk_base_afe *afe); 1176746cc85STrevor Wu int mt8195_afe_disable_reg_rw_clk(struct mtk_base_afe *afe); 1186746cc85STrevor Wu 1196746cc85STrevor Wu #endif 120