Lines Matching +full:sel +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
13 #include "clk.h"
31 #define PLL_MISC_CPCON_MASK ((1 << PLL_MISC_CPCON_WIDTH) - 1)
34 #define PLL_MISC_LFCON_MASK ((1 << PLL_MISC_LFCON_WIDTH) - 1)
37 #define PLL_MISC_VCOCON_MASK ((1 << PLL_MISC_VCOCON_WIDTH) - 1)
230 #define pll_readl(offset, p) readl_relaxed(p->clk_base + offset)
231 #define pll_readl_base(p) pll_readl(p->params->base_reg, p)
232 #define pll_readl_misc(p) pll_readl(p->params->misc_reg, p)
233 #define pll_override_readl(offset, p) readl_relaxed(p->pmc + offset)
234 #define pll_readl_sdm_din(p) pll_readl(p->params->sdm_din_reg, p)
235 #define pll_readl_sdm_ctrl(p) pll_readl(p->params->sdm_ctrl_reg, p)
237 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)
238 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)
239 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)
240 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)
241 #define pll_writel_sdm_din(val, p) pll_writel(val, p->params->sdm_din_reg, p)
242 #define pll_writel_sdm_ctrl(val, p) pll_writel(val, p->params->sdm_ctrl_reg, p)
244 #define mask(w) ((1 << (w)) - 1)
245 #define divm_mask(p) mask(p->params->div_nmp->divm_width)
246 #define divn_mask(p) mask(p->params->div_nmp->divn_width)
247 #define divp_mask(p) (p->params->flags & TEGRA_PLLU ? PLLU_POST_DIVP_MASK :\
248 mask(p->params->div_nmp->divp_width))
249 #define sdm_din_mask(p) p->params->sdm_din_mask
250 #define sdm_en_mask(p) p->params->sdm_ctrl_en_mask
252 #define divm_shift(p) (p)->params->div_nmp->divm_shift
253 #define divn_shift(p) (p)->params->div_nmp->divn_shift
254 #define divp_shift(p) (p)->params->div_nmp->divp_shift
280 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) in clk_pll_enable_lock()
283 if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE)) in clk_pll_enable_lock()
287 val |= BIT(pll->params->lock_enable_bit_idx); in clk_pll_enable_lock()
297 if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) { in clk_pll_wait_for_lock()
298 udelay(pll->params->lock_delay); in clk_pll_wait_for_lock()
302 lock_addr = pll->clk_base; in clk_pll_wait_for_lock()
303 if (pll->params->flags & TEGRA_PLL_LOCK_MISC) in clk_pll_wait_for_lock()
304 lock_addr += pll->params->misc_reg; in clk_pll_wait_for_lock()
306 lock_addr += pll->params->base_reg; in clk_pll_wait_for_lock()
308 lock_mask = pll->params->lock_mask; in clk_pll_wait_for_lock()
310 for (i = 0; i < pll->params->lock_delay; i++) { in clk_pll_wait_for_lock()
320 clk_hw_get_name(&pll->hw)); in clk_pll_wait_for_lock()
322 return -1; in clk_pll_wait_for_lock()
332 u32 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in pllm_clk_is_gated_by_pmc()
345 * settings, including the enable-state. The PLLM is enabled when in clk_pll_is_enabled()
348 if ((pll->params->flags & TEGRA_PLLM) && pllm_clk_is_gated_by_pmc(pll)) in clk_pll_is_enabled()
361 if (pll->params->iddq_reg) { in _clk_pll_enable()
362 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_enable()
363 val &= ~BIT(pll->params->iddq_bit_idx); in _clk_pll_enable()
364 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_enable()
368 if (pll->params->reset_reg) { in _clk_pll_enable()
369 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_enable()
370 val &= ~BIT(pll->params->reset_bit_idx); in _clk_pll_enable()
371 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_enable()
377 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_enable()
382 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_enable()
383 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
385 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_enable()
395 if (pll->params->flags & TEGRA_PLL_BYPASS) in _clk_pll_disable()
400 if (pll->params->flags & TEGRA_PLLM) { in _clk_pll_disable()
401 val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
403 writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE); in _clk_pll_disable()
406 if (pll->params->reset_reg) { in _clk_pll_disable()
407 val = pll_readl(pll->params->reset_reg, pll); in _clk_pll_disable()
408 val |= BIT(pll->params->reset_bit_idx); in _clk_pll_disable()
409 pll_writel(val, pll->params->reset_reg, pll); in _clk_pll_disable()
412 if (pll->params->iddq_reg) { in _clk_pll_disable()
413 val = pll_readl(pll->params->iddq_reg, pll); in _clk_pll_disable()
414 val |= BIT(pll->params->iddq_bit_idx); in _clk_pll_disable()
415 pll_writel(val, pll->params->iddq_reg, pll); in _clk_pll_disable()
422 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_start_ss()
423 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
425 val |= pll->params->ssc_ctrl_en_mask; in pll_clk_start_ss()
426 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_start_ss()
432 if (pll->params->defaults_set && pll->params->ssc_ctrl_reg) { in pll_clk_stop_ss()
433 u32 val = pll_readl(pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
435 val &= ~pll->params->ssc_ctrl_en_mask; in pll_clk_stop_ss()
436 pll_writel(val, pll->params->ssc_ctrl_reg, pll); in pll_clk_stop_ss()
449 if (pll->lock) in clk_pll_enable()
450 spin_lock_irqsave(pll->lock, flags); in clk_pll_enable()
458 if (pll->lock) in clk_pll_enable()
459 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_enable()
469 if (pll->lock) in clk_pll_disable()
470 spin_lock_irqsave(pll->lock, flags); in clk_pll_disable()
476 if (pll->lock) in clk_pll_disable()
477 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_disable()
483 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _p_div_to_hw()
486 while (p_tohw->pdiv) { in _p_div_to_hw()
487 if (p_div <= p_tohw->pdiv) in _p_div_to_hw()
488 return p_tohw->hw_val; in _p_div_to_hw()
491 return -EINVAL; in _p_div_to_hw()
493 return -EINVAL; in _p_div_to_hw()
498 return _p_div_to_hw(&pll->hw, p_div); in tegra_pll_p_div_to_hw()
504 const struct pdiv_map *p_tohw = pll->params->pdiv_tohw; in _hw_to_p_div()
507 while (p_tohw->pdiv) { in _hw_to_p_div()
508 if (p_div_hw == p_tohw->hw_val) in _hw_to_p_div()
509 return p_tohw->pdiv; in _hw_to_p_div()
512 return -EINVAL; in _hw_to_p_div()
523 struct tegra_clk_pll_freq_table *sel; in _get_table_rate() local
526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
528 sel->output_rate == rate) in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
532 return -EINVAL; in _get_table_rate()
534 if (pll->params->pdiv_tohw) { in _get_table_rate()
535 p = _p_div_to_hw(hw, sel->p); in _get_table_rate()
539 p = ilog2(sel->p); in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
543 cfg->output_rate = sel->output_rate; in _get_table_rate()
544 cfg->m = sel->m; in _get_table_rate()
545 cfg->n = sel->n; in _get_table_rate()
546 cfg->p = p; in _get_table_rate()
547 cfg->cpcon = sel->cpcon; in _get_table_rate()
548 cfg->sdm_data = sel->sdm_data; in _get_table_rate()
562 return -EINVAL; in _calc_rate()
590 for (cfg->output_rate = rate; cfg->output_rate < 200 * cfreq; in _calc_rate()
591 cfg->output_rate <<= 1) in _calc_rate()
594 cfg->m = parent_rate / cfreq; in _calc_rate()
595 cfg->n = cfg->output_rate / cfreq; in _calc_rate()
596 cfg->cpcon = OUT_OF_TABLE_CPCON; in _calc_rate()
598 if (cfg->m == 0 || cfg->m > divm_max(pll) || in _calc_rate()
599 cfg->n > divn_max(pll) || (1 << p_div) > divp_max(pll) || in _calc_rate()
600 cfg->output_rate > pll->params->vco_max) { in _calc_rate()
601 return -EINVAL; in _calc_rate()
604 cfg->output_rate = cfg->n * DIV_ROUND_UP(parent_rate, cfg->m); in _calc_rate()
605 cfg->output_rate >>= p_div; in _calc_rate()
607 if (pll->params->pdiv_tohw) { in _calc_rate()
612 cfg->p = ret; in _calc_rate()
614 cfg->p = p_div; in _calc_rate()
620 * SDM (Sigma Delta Modulator) divisor is 16-bit 2's complement signed number
621 * within (-2^12 ... 2^12-1) range. Represented in PLL data structure as
622 * unsigned 16-bit value, with "0" divisor mapped to 0xFFFF. Data "0" is used
634 if (!pll->params->sdm_din_reg) in clk_pll_set_sdm_data()
637 if (cfg->sdm_data) { in clk_pll_set_sdm_data()
639 val |= sdin_data_to_din(cfg->sdm_data) & sdm_din_mask(pll); in clk_pll_set_sdm_data()
646 if (cfg->sdm_data == 0 && enabled) in clk_pll_set_sdm_data()
647 val &= ~pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
649 if (cfg->sdm_data != 0 && !enabled) in clk_pll_set_sdm_data()
650 val |= pll->params->sdm_ctrl_en_mask; in clk_pll_set_sdm_data()
659 struct tegra_clk_pll_params *params = pll->params; in _update_pll_mnp()
660 struct div_nmp *div_nmp = params->div_nmp; in _update_pll_mnp()
662 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in _update_pll_mnp()
665 val = pll_override_readl(params->pmc_divp_reg, pll); in _update_pll_mnp()
666 val &= ~(divp_mask(pll) << div_nmp->override_divp_shift); in _update_pll_mnp()
667 val |= cfg->p << div_nmp->override_divp_shift; in _update_pll_mnp()
668 pll_override_writel(val, params->pmc_divp_reg, pll); in _update_pll_mnp()
670 val = pll_override_readl(params->pmc_divnm_reg, pll); in _update_pll_mnp()
671 val &= ~((divm_mask(pll) << div_nmp->override_divm_shift) | in _update_pll_mnp()
672 (divn_mask(pll) << div_nmp->override_divn_shift)); in _update_pll_mnp()
673 val |= (cfg->m << div_nmp->override_divm_shift) | in _update_pll_mnp()
674 (cfg->n << div_nmp->override_divn_shift); in _update_pll_mnp()
675 pll_override_writel(val, params->pmc_divnm_reg, pll); in _update_pll_mnp()
682 val |= (cfg->m << divm_shift(pll)) | in _update_pll_mnp()
683 (cfg->n << divn_shift(pll)) | in _update_pll_mnp()
684 (cfg->p << divp_shift(pll)); in _update_pll_mnp()
688 clk_pll_set_sdm_data(&pll->hw, cfg); in _update_pll_mnp()
696 struct tegra_clk_pll_params *params = pll->params; in _get_pll_mnp()
697 struct div_nmp *div_nmp = params->div_nmp; in _get_pll_mnp()
701 if ((params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in _get_pll_mnp()
704 val = pll_override_readl(params->pmc_divp_reg, pll); in _get_pll_mnp()
705 cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll); in _get_pll_mnp()
707 val = pll_override_readl(params->pmc_divnm_reg, pll); in _get_pll_mnp()
708 cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll); in _get_pll_mnp()
709 cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll); in _get_pll_mnp()
713 cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll); in _get_pll_mnp()
714 cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll); in _get_pll_mnp()
715 cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll); in _get_pll_mnp()
717 if (pll->params->sdm_din_reg) { in _get_pll_mnp()
721 cfg->sdm_data = sdin_din_to_data(val); in _get_pll_mnp()
736 val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT; in _update_pll_cpcon()
738 if (pll->params->flags & TEGRA_PLL_SET_LFCON) { in _update_pll_cpcon()
740 if (cfg->n >= PLLDU_LFCON_SET_DIVN) in _update_pll_cpcon()
742 } else if (pll->params->flags & TEGRA_PLL_SET_DCCON) { in _update_pll_cpcon()
744 if (rate >= (pll->params->vco_max >> 1)) in _update_pll_cpcon()
760 if (state && pll->params->pre_rate_change) { in _program_pll()
761 ret = pll->params->pre_rate_change(); in _program_pll()
768 if (state && pll->params->defaults_set && pll->params->dyn_ramp && in _program_pll()
769 (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { in _program_pll()
770 ret = pll->params->dyn_ramp(pll, cfg); in _program_pll()
780 if (!pll->params->defaults_set && pll->params->set_defaults) in _program_pll()
781 pll->params->set_defaults(pll); in _program_pll()
785 if (pll->params->flags & TEGRA_PLL_HAS_CPCON) in _program_pll()
795 if (state && pll->params->post_rate_change) in _program_pll()
796 pll->params->post_rate_change(); in _program_pll()
809 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_set_rate()
810 if (rate != pll->params->fixed_rate) { in clk_pll_set_rate()
813 pll->params->fixed_rate, rate); in clk_pll_set_rate()
814 return -EINVAL; in clk_pll_set_rate()
820 pll->params->calc_rate(hw, &cfg, rate, parent_rate)) { in clk_pll_set_rate()
824 return -EINVAL; in clk_pll_set_rate()
826 if (pll->lock) in clk_pll_set_rate()
827 spin_lock_irqsave(pll->lock, flags); in clk_pll_set_rate()
830 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pll_set_rate()
837 if (pll->lock) in clk_pll_set_rate()
838 spin_unlock_irqrestore(pll->lock, flags); in clk_pll_set_rate()
849 if (pll->params->flags & TEGRA_PLL_FIXED) { in clk_pll_determine_rate()
851 if (pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) in clk_pll_determine_rate()
852 req->rate = clk_hw_get_rate(hw); in clk_pll_determine_rate()
854 req->rate = pll->params->fixed_rate; in clk_pll_determine_rate()
859 if (_get_table_rate(hw, &cfg, req->rate, req->best_parent_rate) && in clk_pll_determine_rate()
860 pll->params->calc_rate(hw, &cfg, req->rate, req->best_parent_rate)) in clk_pll_determine_rate()
861 return -EINVAL; in clk_pll_determine_rate()
863 req->rate = cfg.output_rate; in clk_pll_determine_rate()
879 if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS)) in clk_pll_recalc_rate()
882 if ((pll->params->flags & TEGRA_PLL_FIXED) && in clk_pll_recalc_rate()
883 !(pll->params->flags & (TEGRA_PLLM | TEGRA_PLLMB)) && in clk_pll_recalc_rate()
885 struct tegra_clk_pll_freq_table sel; in clk_pll_recalc_rate() local
886 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, in clk_pll_recalc_rate()
892 return pll->params->fixed_rate; in clk_pll_recalc_rate()
897 if (pll->params->flags & TEGRA_PLL_VCO_OUT) { in clk_pll_recalc_rate()
908 if (pll->params->set_gain) in clk_pll_recalc_rate()
909 pll->params->set_gain(&cfg); in clk_pll_recalc_rate()
924 if (!pll->pmc) in clk_plle_training()
925 return -ENOSYS; in clk_plle_training()
931 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
933 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
935 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
937 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
939 val = readl(pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
941 writel(val, pll->pmc + PMC_SATA_PWRGT); in clk_plle_training()
952 return -EBUSY; in clk_plle_training()
963 struct tegra_clk_pll_freq_table sel; in clk_plle_enable() local
973 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
974 return -EINVAL; in clk_plle_enable()
989 if (pll->params->flags & TEGRA_PLLE_CONFIGURE) { in clk_plle_enable()
995 val |= sel.m << divm_shift(pll); in clk_plle_enable()
996 val |= sel.n << divn_shift(pll); in clk_plle_enable()
997 val |= sel.p << divp_shift(pll); in clk_plle_enable()
998 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; in clk_plle_enable()
1007 val = readl(pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1010 writel(val, pll->clk_base + PLLE_SS_CTRL); in clk_plle_enable()
1029 divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll)); in clk_plle_recalc_rate()
1030 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1031 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); in clk_plle_recalc_rate()
1049 if (pll->params->set_defaults) in tegra_clk_pll_restore_context()
1050 pll->params->set_defaults(pll); in tegra_clk_pll_restore_context()
1054 if (!__clk_get_enable_count(hw->clk)) in tegra_clk_pll_restore_context()
1134 return -EINVAL; in clk_pllu_enable()
1139 if (pll->lock) in clk_pllu_enable()
1140 spin_lock_irqsave(pll->lock, flags); in clk_pllu_enable()
1159 ret = -EINVAL; in clk_pllu_enable()
1167 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1170 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); in clk_pllu_enable()
1172 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); in clk_pllu_enable()
1177 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_enable()
1179 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1182 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_enable()
1184 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); in clk_pllu_enable()
1189 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_enable()
1192 if (pll->lock) in clk_pllu_enable()
1193 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_enable()
1210 u16 mdiv = parent_rate / pll_params->cf_min; in _pll_fixed_mdiv()
1212 if (pll_params->flags & TEGRA_MDIV_NEW) in _pll_fixed_mdiv()
1213 return (!pll_params->mdiv_default ? mdiv : in _pll_fixed_mdiv()
1214 min(mdiv, pll_params->mdiv_default)); in _pll_fixed_mdiv()
1216 if (pll_params->mdiv_default) in _pll_fixed_mdiv()
1217 return pll_params->mdiv_default; in _pll_fixed_mdiv()
1219 if (parent_rate > pll_params->cf_max) in _pll_fixed_mdiv()
1234 return -EINVAL; in _calc_dynamic_ramp_rate()
1236 p = DIV_ROUND_UP(pll->params->vco_min, rate); in _calc_dynamic_ramp_rate()
1237 cfg->m = _pll_fixed_mdiv(pll->params, parent_rate); in _calc_dynamic_ramp_rate()
1238 cfg->output_rate = rate * p; in _calc_dynamic_ramp_rate()
1239 cfg->n = cfg->output_rate * cfg->m / parent_rate; in _calc_dynamic_ramp_rate()
1240 cfg->input_rate = parent_rate; in _calc_dynamic_ramp_rate()
1246 cfg->p = p_div; in _calc_dynamic_ramp_rate()
1248 if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max) in _calc_dynamic_ramp_rate()
1249 return -EINVAL; in _calc_dynamic_ramp_rate()
1263 return (u16)_pll_fixed_mdiv(pll->params, input_rate); in tegra_pll_get_fixed_mdiv()
1298 return -EINVAL; in _setup_dynamic_ramp()
1301 val = step_a << pll_params->stepa_shift; in _setup_dynamic_ramp()
1302 val |= step_b << pll_params->stepb_shift; in _setup_dynamic_ramp()
1303 writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg); in _setup_dynamic_ramp()
1319 if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) { in _pll_ramp_calc_pll()
1321 err = -EINVAL; in _pll_ramp_calc_pll()
1326 if (cfg->p > pll->params->max_p) in _pll_ramp_calc_pll()
1327 err = -EINVAL; in _pll_ramp_calc_pll()
1345 if (pll->lock) in clk_pllxc_set_rate()
1346 spin_lock_irqsave(pll->lock, flags); in clk_pllxc_set_rate()
1349 if (pll->params->flags & TEGRA_PLL_VCO_OUT) in clk_pllxc_set_rate()
1355 if (pll->lock) in clk_pllxc_set_rate()
1356 spin_unlock_irqrestore(pll->lock, flags); in clk_pllxc_set_rate()
1367 u64 output_rate = req->best_parent_rate; in clk_pll_ramp_determine_rate()
1369 ret = _pll_ramp_calc_pll(hw, &cfg, req->rate, req->best_parent_rate); in clk_pll_ramp_determine_rate()
1377 if (pll->params->set_gain) in clk_pll_ramp_determine_rate()
1378 pll->params->set_gain(&cfg); in clk_pll_ramp_determine_rate()
1383 req->rate = output_rate; in clk_pll_ramp_determine_rate()
1411 if (pll->lock) in clk_pllc_enable()
1412 spin_lock_irqsave(pll->lock, flags); in clk_pllc_enable()
1426 if (pll->lock) in clk_pllc_enable()
1427 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_enable()
1450 if (pll->lock) in clk_pllc_disable()
1451 spin_lock_irqsave(pll->lock, flags); in clk_pllc_disable()
1455 if (pll->lock) in clk_pllc_disable()
1456 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_disable()
1481 return -EINVAL; in _pllcx_update_dynamic_coef()
1501 if (pll->lock) in clk_pllc_set_rate()
1502 spin_lock_irqsave(pll->lock, flags); in clk_pllc_set_rate()
1532 if (pll->lock) in clk_pllc_set_rate()
1533 spin_unlock_irqrestore(pll->lock, flags); in clk_pllc_set_rate()
1545 m = _pll_fixed_mdiv(pll->params, parent_rate); in _pllre_calc_rate()
1552 cfg->m = m; in _pllre_calc_rate()
1553 cfg->n = n; in _pllre_calc_rate()
1567 if (pll->lock) in clk_pllre_set_rate()
1568 spin_lock_irqsave(pll->lock, flags); in clk_pllre_set_rate()
1587 if (pll->lock) in clk_pllre_set_rate()
1588 spin_unlock_irqrestore(pll->lock, flags); in clk_pllre_set_rate()
1613 req->rate = _pllre_calc_rate(pll, NULL, req->rate, in clk_pllre_determine_rate()
1614 req->best_parent_rate); in clk_pllre_determine_rate()
1622 struct tegra_clk_pll_freq_table sel; in clk_plle_tegra114_enable() local
1630 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra114_enable()
1631 return -EINVAL; in clk_plle_tegra114_enable()
1633 if (pll->lock) in clk_plle_tegra114_enable()
1634 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_enable()
1640 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1643 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1663 val |= sel.m << divm_shift(pll); in clk_plle_tegra114_enable()
1664 val |= sel.n << divn_shift(pll); in clk_plle_tegra114_enable()
1665 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; in clk_plle_tegra114_enable()
1692 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1695 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1698 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra114_enable()
1724 if (pll->lock) in clk_plle_tegra114_enable()
1725 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_enable()
1736 if (pll->lock) in clk_plle_tegra114_disable()
1737 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra114_disable()
1746 if (pll->lock) in clk_plle_tegra114_disable()
1747 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra114_disable()
1754 struct clk *osc = __clk_lookup("osc"); in clk_pllu_tegra114_enable()
1762 return -EINVAL; in clk_pllu_tegra114_enable()
1767 if (pll->lock) in clk_pllu_tegra114_enable()
1768 spin_lock_irqsave(pll->lock, flags); in clk_pllu_tegra114_enable()
1787 ret = -EINVAL; in clk_pllu_tegra114_enable()
1795 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1798 value |= UTMIP_PLL_CFG2_STABLE_COUNT(params->stable_count); in clk_pllu_tegra114_enable()
1800 value |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(params->active_delay_count); in clk_pllu_tegra114_enable()
1805 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG2); in clk_pllu_tegra114_enable()
1807 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1810 value |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(params->enable_delay_count); in clk_pllu_tegra114_enable()
1812 value |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(params->xtal_freq_count); in clk_pllu_tegra114_enable()
1818 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1821 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1825 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1827 value = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1830 writel_relaxed(value, pll->clk_base + UTMIP_PLL_CFG1); in clk_pllu_tegra114_enable()
1838 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1841 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1846 value = readl_relaxed(pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1848 writel_relaxed(value, pll->clk_base + UTMIPLL_HW_PWRDN_CFG0); in clk_pllu_tegra114_enable()
1851 if (pll->lock) in clk_pllu_tegra114_enable()
1852 spin_unlock_irqrestore(pll->lock, flags); in clk_pllu_tegra114_enable()
1863 val_aux = pll_readl(pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1873 pll_writel(val_aux, pll->params->aux_reg, pll); in _clk_plle_tegra_init_parent()
1874 fence_udelay(1, pll->clk_base); in _clk_plle_tegra_init_parent()
1887 return ERR_PTR(-ENOMEM); in _tegra_init_pll()
1889 pll->clk_base = clk_base; in _tegra_init_pll()
1890 pll->pmc = pmc; in _tegra_init_pll()
1892 pll->params = pll_params; in _tegra_init_pll()
1893 pll->lock = lock; in _tegra_init_pll()
1895 if (!pll_params->div_nmp) in _tegra_init_pll()
1896 pll_params->div_nmp = &default_nmp; in _tegra_init_pll()
1901 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll, in _tegra_clk_register_pll()
1914 if (!pll->params->calc_rate) { in _tegra_clk_register_pll()
1915 if (pll->params->flags & TEGRA_PLLM) in _tegra_clk_register_pll()
1916 pll->params->calc_rate = _calc_dynamic_ramp_rate; in _tegra_clk_register_pll()
1918 pll->params->calc_rate = _calc_rate; in _tegra_clk_register_pll()
1921 if (pll->params->set_defaults) in _tegra_clk_register_pll()
1922 pll->params->set_defaults(pll); in _tegra_clk_register_pll()
1925 pll->hw.init = &init; in _tegra_clk_register_pll()
1927 return tegra_clk_dev_register(&pll->hw); in _tegra_clk_register_pll()
1930 struct clk *tegra_clk_register_pll(const char *name, const char *parent_name, in tegra_clk_register_pll()
1936 struct clk *clk; in tegra_clk_register_pll() local
1938 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pll()
1944 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pll()
1946 if (IS_ERR(clk)) in tegra_clk_register_pll()
1949 return clk; in tegra_clk_register_pll()
1961 struct clk *tegra_clk_register_plle(const char *name, const char *parent_name, in tegra_clk_register_plle()
1967 struct clk *clk; in tegra_clk_register_plle() local
1969 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_plle()
1971 if (!pll_params->div_nmp) in tegra_clk_register_plle()
1972 pll_params->div_nmp = &pll_e_nmp; in tegra_clk_register_plle()
1978 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle()
1980 if (IS_ERR(clk)) in tegra_clk_register_plle()
1983 return clk; in tegra_clk_register_plle()
1986 struct clk *tegra_clk_register_pllu(const char *name, const char *parent_name, in tegra_clk_register_pllu()
1991 struct clk *clk; in tegra_clk_register_pllu() local
1993 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu()
1999 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllu()
2001 if (IS_ERR(clk)) in tegra_clk_register_pllu()
2004 return clk; in tegra_clk_register_pllu()
2052 struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name, in tegra_clk_register_pllxc()
2059 struct clk *clk, *parent; in tegra_clk_register_pllxc() local
2065 WARN(1, "parent clk %s of %s must be registered first\n", in tegra_clk_register_pllxc()
2067 return ERR_PTR(-EINVAL); in tegra_clk_register_pllxc()
2070 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllxc()
2071 return ERR_PTR(-EINVAL); in tegra_clk_register_pllxc()
2075 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllxc()
2077 if (pll_params->adjust_vco) in tegra_clk_register_pllxc()
2078 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllxc()
2085 if (!pll_params->set_defaults) { in tegra_clk_register_pllxc()
2092 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllxc()
2093 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2096 WARN_ON(val_iddq & BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllxc()
2098 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllxc()
2100 clk_base + pll_params->iddq_reg); in tegra_clk_register_pllxc()
2108 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllxc()
2110 if (IS_ERR(clk)) in tegra_clk_register_pllxc()
2113 return clk; in tegra_clk_register_pllxc()
2116 struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name, in tegra_clk_register_pllre()
2124 struct clk *clk; in tegra_clk_register_pllre() local
2126 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre()
2128 if (pll_params->adjust_vco) in tegra_clk_register_pllre()
2129 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre()
2140 WARN_ON(readl_relaxed(clk_base + pll_params->iddq_reg) & in tegra_clk_register_pllre()
2141 BIT(pll_params->iddq_bit_idx)); in tegra_clk_register_pllre()
2147 val |= (pll_params->vco_min / parent_rate) << divn_shift(pll); in tegra_clk_register_pllre()
2157 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllre()
2159 if (IS_ERR(clk)) in tegra_clk_register_pllre()
2162 return clk; in tegra_clk_register_pllre()
2165 struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name, in tegra_clk_register_pllm()
2172 struct clk *clk, *parent; in tegra_clk_register_pllm() local
2175 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllm()
2176 return ERR_PTR(-EINVAL); in tegra_clk_register_pllm()
2180 WARN(1, "parent clk %s of %s must be registered first\n", in tegra_clk_register_pllm()
2182 return ERR_PTR(-EINVAL); in tegra_clk_register_pllm()
2187 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllm()
2189 if (pll_params->adjust_vco) in tegra_clk_register_pllm()
2190 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllm()
2193 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllm()
2194 pll_params->flags |= TEGRA_PLLM; in tegra_clk_register_pllm()
2199 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllm()
2201 if (IS_ERR(clk)) in tegra_clk_register_pllm()
2204 return clk; in tegra_clk_register_pllm()
2207 struct clk *tegra_clk_register_pllc(const char *name, const char *parent_name, in tegra_clk_register_pllc()
2213 struct clk *parent, *clk; in tegra_clk_register_pllc() local
2214 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc()
2220 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2224 WARN(1, "parent clk %s of %s must be registered first\n", in tegra_clk_register_pllc()
2226 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2231 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc()
2233 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc()
2248 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllc()
2250 while (p_tohw->pdiv) { in tegra_clk_register_pllc()
2251 if (p_tohw->pdiv == 2) { in tegra_clk_register_pllc()
2252 cfg.p = p_tohw->hw_val; in tegra_clk_register_pllc()
2258 if (!p_tohw->pdiv) { in tegra_clk_register_pllc()
2260 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc()
2267 pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllc()
2268 pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllc()
2269 pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllc()
2273 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllc()
2275 if (IS_ERR(clk)) in tegra_clk_register_pllc()
2278 return clk; in tegra_clk_register_pllc()
2281 struct clk *tegra_clk_register_plle_tegra114(const char *name, in tegra_clk_register_plle_tegra114()
2288 struct clk *clk; in tegra_clk_register_plle_tegra114() local
2296 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle_tegra114()
2298 if (IS_ERR(clk)) in tegra_clk_register_plle_tegra114()
2301 return clk; in tegra_clk_register_plle_tegra114()
2304 struct clk *
2311 struct clk *clk; in tegra_clk_register_pllu_tegra114() local
2313 pll_params->flags |= TEGRA_PLLU; in tegra_clk_register_pllu_tegra114()
2319 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllu_tegra114()
2321 if (IS_ERR(clk)) in tegra_clk_register_pllu_tegra114()
2324 return clk; in tegra_clk_register_pllu_tegra114()
2339 struct clk *tegra_clk_register_pllss(const char *name, const char *parent_name, in tegra_clk_register_pllss()
2345 struct clk *clk, *parent; in tegra_clk_register_pllss() local
2351 if (!pll_params->div_nmp) in tegra_clk_register_pllss()
2352 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2356 WARN(1, "parent clk %s of %s must be registered first\n", in tegra_clk_register_pllss()
2358 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2371 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss()
2376 cfg.n = cfg.m * pll_params->vco_min / parent_rate; in tegra_clk_register_pllss()
2378 for (i = 0; pll_params->pdiv_tohw[i].pdiv; i++) in tegra_clk_register_pllss()
2382 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2385 cfg.p = pll_params->pdiv_tohw[i-1].hw_val; in tegra_clk_register_pllss()
2390 pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll); in tegra_clk_register_pllss()
2391 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll); in tegra_clk_register_pllss()
2392 pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll); in tegra_clk_register_pllss()
2395 val_iddq = readl_relaxed(clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2397 if (val_iddq & BIT(pll_params->iddq_bit_idx)) { in tegra_clk_register_pllss()
2400 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss()
2403 val_iddq |= BIT(pll_params->iddq_bit_idx); in tegra_clk_register_pllss()
2404 writel_relaxed(val_iddq, clk_base + pll_params->iddq_reg); in tegra_clk_register_pllss()
2410 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllss()
2413 if (IS_ERR(clk)) in tegra_clk_register_pllss()
2416 return clk; in tegra_clk_register_pllss()
2421 struct clk *tegra_clk_register_pllre_tegra210(const char *name, in tegra_clk_register_pllre_tegra210()
2428 struct clk *clk; in tegra_clk_register_pllre_tegra210() local
2430 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllre_tegra210()
2432 if (pll_params->adjust_vco) in tegra_clk_register_pllre_tegra210()
2433 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllre_tegra210()
2440 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllre_tegra210()
2442 if (IS_ERR(clk)) in tegra_clk_register_pllre_tegra210()
2445 return clk; in tegra_clk_register_pllre_tegra210()
2461 struct tegra_clk_pll_freq_table sel; in clk_plle_tegra210_enable() local
2472 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_tegra210_enable()
2473 return -EINVAL; in clk_plle_tegra210_enable()
2475 if (pll->lock) in clk_plle_tegra210_enable()
2476 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_enable()
2478 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_enable()
2503 val |= sel.m << divm_shift(pll); in clk_plle_tegra210_enable()
2504 val |= sel.n << divn_shift(pll); in clk_plle_tegra210_enable()
2505 val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT; in clk_plle_tegra210_enable()
2531 if (pll->lock) in clk_plle_tegra210_enable()
2532 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_enable()
2543 if (pll->lock) in clk_plle_tegra210_disable()
2544 spin_lock_irqsave(pll->lock, flags); in clk_plle_tegra210_disable()
2547 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2555 val = pll_readl(pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2557 pll_writel(val, pll->params->aux_reg, pll); in clk_plle_tegra210_disable()
2565 if (pll->lock) in clk_plle_tegra210_disable()
2566 spin_unlock_irqrestore(pll->lock, flags); in clk_plle_tegra210_disable()
2584 struct clk *tegra_clk_register_plle_tegra210(const char *name, in tegra_clk_register_plle_tegra210()
2591 struct clk *clk; in tegra_clk_register_plle_tegra210() local
2599 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_plle_tegra210()
2601 if (IS_ERR(clk)) in tegra_clk_register_plle_tegra210()
2604 return clk; in tegra_clk_register_plle_tegra210()
2607 struct clk *tegra_clk_register_pllc_tegra210(const char *name, in tegra_clk_register_pllc_tegra210()
2613 struct clk *parent, *clk; in tegra_clk_register_pllc_tegra210() local
2614 const struct pdiv_map *p_tohw = pll_params->pdiv_tohw; in tegra_clk_register_pllc_tegra210()
2619 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc_tegra210()
2623 WARN(1, "parent clk %s of %s must be registered first\n", in tegra_clk_register_pllc_tegra210()
2625 return ERR_PTR(-EINVAL); in tegra_clk_register_pllc_tegra210()
2630 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllc_tegra210()
2632 if (pll_params->adjust_vco) in tegra_clk_register_pllc_tegra210()
2633 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllc_tegra210()
2636 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllc_tegra210()
2641 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllc_tegra210()
2643 if (IS_ERR(clk)) in tegra_clk_register_pllc_tegra210()
2646 return clk; in tegra_clk_register_pllc_tegra210()
2649 struct clk *tegra_clk_register_pllss_tegra210(const char *name, in tegra_clk_register_pllss_tegra210()
2656 struct clk *clk, *parent; in tegra_clk_register_pllss_tegra210() local
2660 if (!pll_params->div_nmp) in tegra_clk_register_pllss_tegra210()
2661 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2665 WARN(1, "parent clk %s of %s must be registered first\n", in tegra_clk_register_pllss_tegra210()
2667 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2670 val = readl_relaxed(clk_base + pll_params->base_reg); in tegra_clk_register_pllss_tegra210()
2673 return ERR_PTR(-EINVAL); in tegra_clk_register_pllss_tegra210()
2678 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllss_tegra210()
2680 if (pll_params->adjust_vco) in tegra_clk_register_pllss_tegra210()
2681 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllss_tegra210()
2684 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllss_tegra210()
2689 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllss_tegra210()
2692 if (IS_ERR(clk)) in tegra_clk_register_pllss_tegra210()
2695 return clk; in tegra_clk_register_pllss_tegra210()
2698 struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name, in tegra_clk_register_pllmb()
2705 struct clk *clk, *parent; in tegra_clk_register_pllmb() local
2708 if (!pll_params->pdiv_tohw) in tegra_clk_register_pllmb()
2709 return ERR_PTR(-EINVAL); in tegra_clk_register_pllmb()
2713 WARN(1, "parent clk %s of %s must be registered first\n", in tegra_clk_register_pllmb()
2715 return ERR_PTR(-EINVAL); in tegra_clk_register_pllmb()
2720 pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate); in tegra_clk_register_pllmb()
2722 if (pll_params->adjust_vco) in tegra_clk_register_pllmb()
2723 pll_params->vco_min = pll_params->adjust_vco(pll_params, in tegra_clk_register_pllmb()
2726 pll_params->flags |= TEGRA_PLL_BYPASS; in tegra_clk_register_pllmb()
2727 pll_params->flags |= TEGRA_PLLMB; in tegra_clk_register_pllmb()
2732 clk = _tegra_clk_register_pll(pll, name, parent_name, flags, in tegra_clk_register_pllmb()
2734 if (IS_ERR(clk)) in tegra_clk_register_pllmb()
2737 return clk; in tegra_clk_register_pllmb()