1fcaf2036SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
211f68120SShawn Guo /*
311f68120SShawn Guo * Copyright 2011-2013 Freescale Semiconductor, Inc.
411f68120SShawn Guo * Copyright 2011 Linaro Ltd.
511f68120SShawn Guo */
611f68120SShawn Guo
711f68120SShawn Guo #include <linux/init.h>
811f68120SShawn Guo #include <linux/types.h>
97d6b5e4fSAnson Huang #include <linux/bits.h>
1011f68120SShawn Guo #include <linux/clk.h>
1111f68120SShawn Guo #include <linux/clkdev.h>
121df37992SStephen Rothwell #include <linux/clk-provider.h>
1311f68120SShawn Guo #include <linux/err.h>
1411f68120SShawn Guo #include <linux/io.h>
15*8bb289bbSOleksij Rempel #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
1611f68120SShawn Guo #include <linux/of.h>
1711f68120SShawn Guo #include <linux/of_address.h>
1811f68120SShawn Guo #include <linux/of_irq.h>
1911f68120SShawn Guo #include <soc/imx/revision.h>
2011f68120SShawn Guo #include <dt-bindings/clock/imx6qdl-clock.h>
2111f68120SShawn Guo
2211f68120SShawn Guo #include "clk.h"
2311f68120SShawn Guo
2411f68120SShawn Guo static const char *step_sels[] = { "osc", "pll2_pfd2_396m", };
2511f68120SShawn Guo static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
2611f68120SShawn Guo static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
2711f68120SShawn Guo static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "osc", "dummy", };
2811f68120SShawn Guo static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", };
2911f68120SShawn Guo static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
3011f68120SShawn Guo static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
3111f68120SShawn Guo static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
3211f68120SShawn Guo static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
3311f68120SShawn Guo static const char *gpu_axi_sels[] = { "axi", "ahb", };
34ee360274SBai Ping static const char *pre_axi_sels[] = { "axi", "ahb", };
3511f68120SShawn Guo static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
36ee360274SBai Ping static const char *gpu2d_core_sels_2[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",};
3711f68120SShawn Guo static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
3811f68120SShawn Guo static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
3911f68120SShawn Guo static const char *ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
4011f68120SShawn Guo static const char *ldb_di_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
4111f68120SShawn Guo static const char *ipu_di_pre_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
4211f68120SShawn Guo static const char *ipu1_di0_sels[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
4311f68120SShawn Guo static const char *ipu1_di1_sels[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
4411f68120SShawn Guo static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
4511f68120SShawn Guo static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
46ee360274SBai Ping static const char *ipu1_di0_sels_2[] = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
47ee360274SBai Ping static const char *ipu1_di1_sels_2[] = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
48ee360274SBai Ping static const char *ipu2_di0_sels_2[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
49ee360274SBai Ping static const char *ipu2_di1_sels_2[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
5011f68120SShawn Guo static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", };
5111f68120SShawn Guo static const char *pcie_axi_sels[] = { "axi", "ahb", };
5211f68120SShawn Guo static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
5311f68120SShawn Guo static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
5411f68120SShawn Guo static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
55ee360274SBai Ping static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", };
5611f68120SShawn Guo static const char *eim_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
5711f68120SShawn Guo static const char *eim_slow_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
5811f68120SShawn Guo static const char *vdo_axi_sels[] = { "axi", "ahb", };
5911f68120SShawn Guo static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
60ee360274SBai Ping static const char *uart_sels[] = { "pll3_80m", "osc", };
61ee360274SBai Ping static const char *ipg_per_sels[] = { "ipg", "osc", };
62ee360274SBai Ping static const char *ecspi_sels[] = { "pll3_60m", "osc", };
63ee360274SBai Ping static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", };
6411f68120SShawn Guo static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
65a7047564SPhilipp Puschmann "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
6611f68120SShawn Guo "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
6711f68120SShawn Guo static const char *cko2_sels[] = {
6811f68120SShawn Guo "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
6911f68120SShawn Guo "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
7011f68120SShawn Guo "usdhc3", "dummy", "arm", "ipu1",
7111f68120SShawn Guo "ipu2", "vdo_axi", "osc", "gpu2d_core",
7211f68120SShawn Guo "gpu3d_core", "usdhc2", "ssi1", "ssi2",
7311f68120SShawn Guo "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
7411f68120SShawn Guo "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
7511f68120SShawn Guo "uart_serial", "spdif", "asrc", "hsi_tx",
7611f68120SShawn Guo };
7711f68120SShawn Guo static const char *cko_sels[] = { "cko1", "cko2", };
7811f68120SShawn Guo static const char *lvds_sels[] = {
7911f68120SShawn Guo "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
8011f68120SShawn Guo "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
812e133f61SMichael Trimarchi "pcie_ref_125m", "sata_ref_100m", "usbphy1", "usbphy2",
822e133f61SMichael Trimarchi "dummy", "dummy", "dummy", "dummy", "osc",
8311f68120SShawn Guo };
8411f68120SShawn Guo static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
8511f68120SShawn Guo static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
8611f68120SShawn Guo static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
8711f68120SShawn Guo static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
8811f68120SShawn Guo static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
8911f68120SShawn Guo static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
9011f68120SShawn Guo static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
9111f68120SShawn Guo static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
9211f68120SShawn Guo
93992b703bSAbel Vesa static struct clk_hw **hws;
94992b703bSAbel Vesa static struct clk_hw_onecell_data *clk_hw_data;
9511f68120SShawn Guo
9611f68120SShawn Guo static struct clk_div_table clk_enet_ref_table[] = {
9711f68120SShawn Guo { .val = 0, .div = 20, },
9811f68120SShawn Guo { .val = 1, .div = 10, },
9911f68120SShawn Guo { .val = 2, .div = 5, },
10011f68120SShawn Guo { .val = 3, .div = 4, },
10111f68120SShawn Guo { /* sentinel */ }
10211f68120SShawn Guo };
10311f68120SShawn Guo
10411f68120SShawn Guo static struct clk_div_table post_div_table[] = {
10511f68120SShawn Guo { .val = 2, .div = 1, },
10611f68120SShawn Guo { .val = 1, .div = 2, },
10711f68120SShawn Guo { .val = 0, .div = 4, },
10811f68120SShawn Guo { /* sentinel */ }
10911f68120SShawn Guo };
11011f68120SShawn Guo
11111f68120SShawn Guo static struct clk_div_table video_div_table[] = {
11211f68120SShawn Guo { .val = 0, .div = 1, },
11311f68120SShawn Guo { .val = 1, .div = 2, },
11411f68120SShawn Guo { .val = 2, .div = 1, },
11511f68120SShawn Guo { .val = 3, .div = 4, },
11611f68120SShawn Guo { /* sentinel */ }
11711f68120SShawn Guo };
11811f68120SShawn Guo
119*8bb289bbSOleksij Rempel static const char * enet_ref_sels[] = { "enet_ref", "enet_ref_pad", };
120*8bb289bbSOleksij Rempel static const u32 enet_ref_sels_table[] = { IMX6Q_GPR1_ENET_CLK_SEL_ANATOP, IMX6Q_GPR1_ENET_CLK_SEL_PAD };
121*8bb289bbSOleksij Rempel static const u32 enet_ref_sels_table_mask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
122*8bb289bbSOleksij Rempel
12311f68120SShawn Guo static unsigned int share_count_esai;
12411f68120SShawn Guo static unsigned int share_count_asrc;
12511f68120SShawn Guo static unsigned int share_count_ssi1;
12611f68120SShawn Guo static unsigned int share_count_ssi2;
12711f68120SShawn Guo static unsigned int share_count_ssi3;
12811f68120SShawn Guo static unsigned int share_count_mipi_core_cfg;
12984a87250SShengjiu Wang static unsigned int share_count_spdif;
130ee360274SBai Ping static unsigned int share_count_prg0;
131ee360274SBai Ping static unsigned int share_count_prg1;
13211f68120SShawn Guo
clk_on_imx6q(void)13311f68120SShawn Guo static inline int clk_on_imx6q(void)
13411f68120SShawn Guo {
13511f68120SShawn Guo return of_machine_is_compatible("fsl,imx6q");
13611f68120SShawn Guo }
13711f68120SShawn Guo
clk_on_imx6qp(void)138ee360274SBai Ping static inline int clk_on_imx6qp(void)
139ee360274SBai Ping {
140ee360274SBai Ping return of_machine_is_compatible("fsl,imx6qp");
141ee360274SBai Ping }
142ee360274SBai Ping
clk_on_imx6dl(void)14311f68120SShawn Guo static inline int clk_on_imx6dl(void)
14411f68120SShawn Guo {
14511f68120SShawn Guo return of_machine_is_compatible("fsl,imx6dl");
14611f68120SShawn Guo }
14711f68120SShawn Guo
ldb_di_sel_by_clock_id(int clock_id)1485d283b08SFabio Estevam static int ldb_di_sel_by_clock_id(int clock_id)
1495d283b08SFabio Estevam {
1505d283b08SFabio Estevam switch (clock_id) {
1515d283b08SFabio Estevam case IMX6QDL_CLK_PLL5_VIDEO_DIV:
1525d283b08SFabio Estevam if (clk_on_imx6q() &&
1535d283b08SFabio Estevam imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
1545d283b08SFabio Estevam return -ENOENT;
1555d283b08SFabio Estevam return 0;
1565d283b08SFabio Estevam case IMX6QDL_CLK_PLL2_PFD0_352M:
1575d283b08SFabio Estevam return 1;
1585d283b08SFabio Estevam case IMX6QDL_CLK_PLL2_PFD2_396M:
1595d283b08SFabio Estevam return 2;
1605d283b08SFabio Estevam case IMX6QDL_CLK_MMDC_CH1_AXI:
1615d283b08SFabio Estevam return 3;
1625d283b08SFabio Estevam case IMX6QDL_CLK_PLL3_USB_OTG:
1635d283b08SFabio Estevam return 4;
1645d283b08SFabio Estevam default:
1655d283b08SFabio Estevam return -ENOENT;
1665d283b08SFabio Estevam }
1675d283b08SFabio Estevam }
1685d283b08SFabio Estevam
of_assigned_ldb_sels(struct device_node * node,unsigned int * ldb_di0_sel,unsigned int * ldb_di1_sel)1695d283b08SFabio Estevam static void of_assigned_ldb_sels(struct device_node *node,
1705d283b08SFabio Estevam unsigned int *ldb_di0_sel,
1715d283b08SFabio Estevam unsigned int *ldb_di1_sel)
1725d283b08SFabio Estevam {
1735d283b08SFabio Estevam struct of_phandle_args clkspec;
1745d283b08SFabio Estevam int index, rc, num_parents;
1755d283b08SFabio Estevam int parent, child, sel;
1765d283b08SFabio Estevam
1775d283b08SFabio Estevam num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
1785d283b08SFabio Estevam "#clock-cells");
1795d283b08SFabio Estevam for (index = 0; index < num_parents; index++) {
1805d283b08SFabio Estevam rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
1815d283b08SFabio Estevam "#clock-cells", index, &clkspec);
1825d283b08SFabio Estevam if (rc < 0) {
1835d283b08SFabio Estevam /* skip empty (null) phandles */
1845d283b08SFabio Estevam if (rc == -ENOENT)
1855d283b08SFabio Estevam continue;
1865d283b08SFabio Estevam else
1875d283b08SFabio Estevam return;
1885d283b08SFabio Estevam }
1895d283b08SFabio Estevam if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
1905d283b08SFabio Estevam pr_err("ccm: parent clock %d not in ccm\n", index);
1915d283b08SFabio Estevam return;
1925d283b08SFabio Estevam }
1935d283b08SFabio Estevam parent = clkspec.args[0];
1945d283b08SFabio Estevam
1955d283b08SFabio Estevam rc = of_parse_phandle_with_args(node, "assigned-clocks",
1965d283b08SFabio Estevam "#clock-cells", index, &clkspec);
1975d283b08SFabio Estevam if (rc < 0)
1985d283b08SFabio Estevam return;
1995d283b08SFabio Estevam if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
2005d283b08SFabio Estevam pr_err("ccm: child clock %d not in ccm\n", index);
2015d283b08SFabio Estevam return;
2025d283b08SFabio Estevam }
2035d283b08SFabio Estevam child = clkspec.args[0];
2045d283b08SFabio Estevam
2055d283b08SFabio Estevam if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
2065d283b08SFabio Estevam child != IMX6QDL_CLK_LDB_DI1_SEL)
2075d283b08SFabio Estevam continue;
2085d283b08SFabio Estevam
2095d283b08SFabio Estevam sel = ldb_di_sel_by_clock_id(parent);
2105d283b08SFabio Estevam if (sel < 0) {
2115d283b08SFabio Estevam pr_err("ccm: invalid ldb_di%d parent clock: %d\n",
2125d283b08SFabio Estevam child == IMX6QDL_CLK_LDB_DI1_SEL, parent);
2135d283b08SFabio Estevam continue;
2145d283b08SFabio Estevam }
2155d283b08SFabio Estevam
2165d283b08SFabio Estevam if (child == IMX6QDL_CLK_LDB_DI0_SEL)
2175d283b08SFabio Estevam *ldb_di0_sel = sel;
2185d283b08SFabio Estevam if (child == IMX6QDL_CLK_LDB_DI1_SEL)
2195d283b08SFabio Estevam *ldb_di1_sel = sel;
2205d283b08SFabio Estevam }
2215d283b08SFabio Estevam }
2225d283b08SFabio Estevam
pll6_bypassed(struct device_node * node)2233cc48976SLucas Stach static bool pll6_bypassed(struct device_node *node)
2243cc48976SLucas Stach {
2253cc48976SLucas Stach int index, ret, num_clocks;
2263cc48976SLucas Stach struct of_phandle_args clkspec;
2273cc48976SLucas Stach
2283cc48976SLucas Stach num_clocks = of_count_phandle_with_args(node, "assigned-clocks",
2293cc48976SLucas Stach "#clock-cells");
2303cc48976SLucas Stach if (num_clocks < 0)
2313cc48976SLucas Stach return false;
2323cc48976SLucas Stach
2333cc48976SLucas Stach for (index = 0; index < num_clocks; index++) {
2343cc48976SLucas Stach ret = of_parse_phandle_with_args(node, "assigned-clocks",
2353cc48976SLucas Stach "#clock-cells", index,
2363cc48976SLucas Stach &clkspec);
2373cc48976SLucas Stach if (ret < 0)
2383cc48976SLucas Stach return false;
2393cc48976SLucas Stach
2403cc48976SLucas Stach if (clkspec.np == node &&
2413cc48976SLucas Stach clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
2423cc48976SLucas Stach break;
2433cc48976SLucas Stach }
2443cc48976SLucas Stach
2453cc48976SLucas Stach /* PLL6 bypass is not part of the assigned clock list */
2463cc48976SLucas Stach if (index == num_clocks)
2473cc48976SLucas Stach return false;
2483cc48976SLucas Stach
2493cc48976SLucas Stach ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
2503cc48976SLucas Stach "#clock-cells", index, &clkspec);
2513cc48976SLucas Stach
2523cc48976SLucas Stach if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
2533cc48976SLucas Stach return true;
2543cc48976SLucas Stach
2553cc48976SLucas Stach return false;
2563cc48976SLucas Stach }
2573cc48976SLucas Stach
2585d283b08SFabio Estevam #define CCM_CCSR 0x0c
2595d283b08SFabio Estevam #define CCM_CS2CDR 0x2c
260f13abeffSPhilipp Zabel
2615d283b08SFabio Estevam #define CCSR_PLL3_SW_CLK_SEL BIT(0)
2625d283b08SFabio Estevam
2635d283b08SFabio Estevam #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT 9
2645d283b08SFabio Estevam #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT 12
265f13abeffSPhilipp Zabel
2665d283b08SFabio Estevam /*
2675d283b08SFabio Estevam * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk
2685d283b08SFabio Estevam * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the
2695d283b08SFabio Estevam * bypass clock source, since there is no CG bit for mmdc_ch1.
2705d283b08SFabio Estevam */
mmdc_ch1_disable(void __iomem * ccm_base)2715d283b08SFabio Estevam static void mmdc_ch1_disable(void __iomem *ccm_base)
2725d283b08SFabio Estevam {
2735d283b08SFabio Estevam unsigned int reg;
2745d283b08SFabio Estevam
275992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk,
276992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
2775d283b08SFabio Estevam
2785d283b08SFabio Estevam /* Disable pll3_sw_clk by selecting the bypass clock source */
2795d283b08SFabio Estevam reg = readl_relaxed(ccm_base + CCM_CCSR);
2805d283b08SFabio Estevam reg |= CCSR_PLL3_SW_CLK_SEL;
2815d283b08SFabio Estevam writel_relaxed(reg, ccm_base + CCM_CCSR);
2825d283b08SFabio Estevam }
2835d283b08SFabio Estevam
mmdc_ch1_reenable(void __iomem * ccm_base)2845d283b08SFabio Estevam static void mmdc_ch1_reenable(void __iomem *ccm_base)
2855d283b08SFabio Estevam {
2865d283b08SFabio Estevam unsigned int reg;
2875d283b08SFabio Estevam
2885d283b08SFabio Estevam /* Enable pll3_sw_clk by disabling the bypass */
2895d283b08SFabio Estevam reg = readl_relaxed(ccm_base + CCM_CCSR);
2905d283b08SFabio Estevam reg &= ~CCSR_PLL3_SW_CLK_SEL;
2915d283b08SFabio Estevam writel_relaxed(reg, ccm_base + CCM_CCSR);
2925d283b08SFabio Estevam }
2935d283b08SFabio Estevam
2945d283b08SFabio Estevam /*
2955d283b08SFabio Estevam * We have to follow a strict procedure when changing the LDB clock source,
2965d283b08SFabio Estevam * otherwise we risk introducing a glitch that can lock up the LDB divider.
2975d283b08SFabio Estevam * Things to keep in mind:
2985d283b08SFabio Estevam *
2995d283b08SFabio Estevam * 1. The current and new parent clock inputs to the mux must be disabled.
3005d283b08SFabio Estevam * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which
3015d283b08SFabio Estevam * has no CG bit.
3025d283b08SFabio Estevam * 3. pll2_pfd2_396m can not be gated if it is used as memory clock.
3035d283b08SFabio Estevam * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four
3045d283b08SFabio Estevam * options are in one mux and the PLL3 option along with three unused
3055d283b08SFabio Estevam * inputs is in a second mux. There is a third mux with two inputs used
3065d283b08SFabio Estevam * to decide between the first and second 4-port mux:
3075d283b08SFabio Estevam *
3085d283b08SFabio Estevam * pll5_video_div 0 --|\
3095d283b08SFabio Estevam * pll2_pfd0_352m 1 --| |_
3105d283b08SFabio Estevam * pll2_pfd2_396m 2 --| | `-|\
3115d283b08SFabio Estevam * mmdc_ch1_axi 3 --|/ | |
3125d283b08SFabio Estevam * | |--
3135d283b08SFabio Estevam * pll3_usb_otg 4 --|\ | |
3145d283b08SFabio Estevam * 5 --| |_,-|/
3155d283b08SFabio Estevam * 6 --| |
3165d283b08SFabio Estevam * 7 --|/
3175d283b08SFabio Estevam *
3185d283b08SFabio Estevam * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
3195d283b08SFabio Estevam * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
3205d283b08SFabio Estevam * switches the parent to the bottom mux first and then manipulates the top
3215d283b08SFabio Estevam * mux to ensure that no glitch will enter the divider.
3225d283b08SFabio Estevam */
init_ldb_clks(struct device_node * np,void __iomem * ccm_base)3235d283b08SFabio Estevam static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
3245d283b08SFabio Estevam {
3255d283b08SFabio Estevam unsigned int reg;
3265d283b08SFabio Estevam unsigned int sel[2][4];
3275d283b08SFabio Estevam int i;
3285d283b08SFabio Estevam
3295d283b08SFabio Estevam reg = readl_relaxed(ccm_base + CCM_CS2CDR);
3305d283b08SFabio Estevam sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7;
3315d283b08SFabio Estevam sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7;
3325d283b08SFabio Estevam
3335d283b08SFabio Estevam sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0];
3345d283b08SFabio Estevam sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0];
3355d283b08SFabio Estevam
3365d283b08SFabio Estevam of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
3375d283b08SFabio Estevam
3385d283b08SFabio Estevam for (i = 0; i < 2; i++) {
339f3afd3fbSAhmad Fatoum /* Print a notice if a glitch might have been introduced already */
3405d283b08SFabio Estevam if (sel[i][0] != 3) {
341f3afd3fbSAhmad Fatoum pr_notice("ccm: possible glitch: ldb_di%d_sel already changed from reset value: %d\n",
3425d283b08SFabio Estevam i, sel[i][0]);
3435d283b08SFabio Estevam }
3445d283b08SFabio Estevam
3455d283b08SFabio Estevam if (sel[i][0] == sel[i][3])
3465d283b08SFabio Estevam continue;
3475d283b08SFabio Estevam
3485d283b08SFabio Estevam /* Only switch to or from pll2_pfd2_396m if it is disabled */
3495d283b08SFabio Estevam if ((sel[i][0] == 2 || sel[i][3] == 2) &&
350992b703bSAbel Vesa (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
351992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) {
3525d283b08SFabio Estevam pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n",
3535d283b08SFabio Estevam i);
3545d283b08SFabio Estevam sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0];
3555d283b08SFabio Estevam continue;
3565d283b08SFabio Estevam }
3575d283b08SFabio Estevam
3585d283b08SFabio Estevam /* First switch to the bottom mux */
3595d283b08SFabio Estevam sel[i][1] = sel[i][0] | 4;
3605d283b08SFabio Estevam
3615d283b08SFabio Estevam /* Then configure the top mux before switching back to it */
3625d283b08SFabio Estevam sel[i][2] = sel[i][3] | 4;
3635d283b08SFabio Estevam
3645d283b08SFabio Estevam pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i,
3655d283b08SFabio Estevam sel[i][0], sel[i][1], sel[i][2], sel[i][3]);
3665d283b08SFabio Estevam }
3675d283b08SFabio Estevam
3685d283b08SFabio Estevam if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3])
3695d283b08SFabio Estevam return;
3705d283b08SFabio Estevam
3715d283b08SFabio Estevam mmdc_ch1_disable(ccm_base);
3725d283b08SFabio Estevam
3735d283b08SFabio Estevam for (i = 1; i < 4; i++) {
3745d283b08SFabio Estevam reg = readl_relaxed(ccm_base + CCM_CS2CDR);
3755d283b08SFabio Estevam reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
3765d283b08SFabio Estevam (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
3775d283b08SFabio Estevam reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
3785d283b08SFabio Estevam (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
3795d283b08SFabio Estevam writel_relaxed(reg, ccm_base + CCM_CS2CDR);
3805d283b08SFabio Estevam }
3815d283b08SFabio Estevam
3825d283b08SFabio Estevam mmdc_ch1_reenable(ccm_base);
3835d283b08SFabio Estevam }
3845d283b08SFabio Estevam
3855d283b08SFabio Estevam #define CCM_ANALOG_PLL_VIDEO 0xa0
3865d283b08SFabio Estevam #define CCM_ANALOG_PFD_480 0xf0
3875d283b08SFabio Estevam #define CCM_ANALOG_PFD_528 0x100
3885d283b08SFabio Estevam
3895d283b08SFabio Estevam #define PLL_ENABLE BIT(13)
3905d283b08SFabio Estevam
3915d283b08SFabio Estevam #define PFD0_CLKGATE BIT(7)
3925d283b08SFabio Estevam #define PFD1_CLKGATE BIT(15)
3935d283b08SFabio Estevam #define PFD2_CLKGATE BIT(23)
3945d283b08SFabio Estevam #define PFD3_CLKGATE BIT(31)
3955d283b08SFabio Estevam
disable_anatop_clocks(void __iomem * anatop_base)3965d283b08SFabio Estevam static void disable_anatop_clocks(void __iomem *anatop_base)
3975d283b08SFabio Estevam {
3985d283b08SFabio Estevam unsigned int reg;
3995d283b08SFabio Estevam
4005d283b08SFabio Estevam /* Make sure PLL2 PFDs 0-2 are gated */
4015d283b08SFabio Estevam reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528);
4025d283b08SFabio Estevam /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */
403992b703bSAbel Vesa if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
404992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)
4055d283b08SFabio Estevam reg |= PFD0_CLKGATE | PFD1_CLKGATE;
4065d283b08SFabio Estevam else
4075d283b08SFabio Estevam reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE;
4085d283b08SFabio Estevam writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528);
4095d283b08SFabio Estevam
4105d283b08SFabio Estevam /* Make sure PLL3 PFDs 0-3 are gated */
4115d283b08SFabio Estevam reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480);
4125d283b08SFabio Estevam reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE;
4135d283b08SFabio Estevam writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480);
4145d283b08SFabio Estevam
4155d283b08SFabio Estevam /* Make sure PLL5 is disabled */
4165d283b08SFabio Estevam reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO);
4175d283b08SFabio Estevam reg &= ~PLL_ENABLE;
4185d283b08SFabio Estevam writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO);
4195d283b08SFabio Estevam }
4205d283b08SFabio Estevam
imx6q_obtain_fixed_clk_hw(struct device_node * np,const char * name,unsigned long rate)4210e12248cSArnd Bergmann static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np,
4220e12248cSArnd Bergmann const char *name,
4230e12248cSArnd Bergmann unsigned long rate)
424992b703bSAbel Vesa {
425992b703bSAbel Vesa struct clk *clk = of_clk_get_by_name(np, name);
426992b703bSAbel Vesa struct clk_hw *hw;
427992b703bSAbel Vesa
428992b703bSAbel Vesa if (IS_ERR(clk))
429992b703bSAbel Vesa hw = imx_obtain_fixed_clock_hw(name, rate);
430992b703bSAbel Vesa else
431992b703bSAbel Vesa hw = __clk_get_hw(clk);
432992b703bSAbel Vesa
433992b703bSAbel Vesa return hw;
434992b703bSAbel Vesa }
435992b703bSAbel Vesa
imx6q_clocks_init(struct device_node * ccm_node)43611f68120SShawn Guo static void __init imx6q_clocks_init(struct device_node *ccm_node)
43711f68120SShawn Guo {
43811f68120SShawn Guo struct device_node *np;
4395d283b08SFabio Estevam void __iomem *anatop_base, *base;
44011f68120SShawn Guo int ret;
44111f68120SShawn Guo
442992b703bSAbel Vesa clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
443992b703bSAbel Vesa IMX6QDL_CLK_END), GFP_KERNEL);
444992b703bSAbel Vesa if (WARN_ON(!clk_hw_data))
445992b703bSAbel Vesa return;
446992b703bSAbel Vesa
447992b703bSAbel Vesa clk_hw_data->num = IMX6QDL_CLK_END;
448992b703bSAbel Vesa hws = clk_hw_data->hws;
449992b703bSAbel Vesa
450992b703bSAbel Vesa hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
451992b703bSAbel Vesa
452992b703bSAbel Vesa hws[IMX6QDL_CLK_CKIL] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckil", 0);
453992b703bSAbel Vesa hws[IMX6QDL_CLK_CKIH] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckih1", 0);
454992b703bSAbel Vesa hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(ccm_node, "osc", 0);
455a29be918SLucas Stach
45611f68120SShawn Guo /* Clock source from external clock via CLK1/2 PADs */
457992b703bSAbel Vesa hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk1", 0);
458992b703bSAbel Vesa hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk2", 0);
45911f68120SShawn Guo
46011f68120SShawn Guo np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
4615d283b08SFabio Estevam anatop_base = base = of_iomap(np, 0);
46211f68120SShawn Guo WARN_ON(!base);
463c9ec1d8fSYangtao Li of_node_put(np);
46411f68120SShawn Guo
46511f68120SShawn Guo /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
46611f68120SShawn Guo if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
46711f68120SShawn Guo post_div_table[1].div = 1;
46811f68120SShawn Guo post_div_table[2].div = 1;
46911f68120SShawn Guo video_div_table[1].div = 1;
47011f68120SShawn Guo video_div_table[3].div = 1;
47111f68120SShawn Guo }
47211f68120SShawn Guo
473992b703bSAbel Vesa hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
474992b703bSAbel Vesa hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
475992b703bSAbel Vesa hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
476992b703bSAbel Vesa hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
477992b703bSAbel Vesa hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
478992b703bSAbel Vesa hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
479992b703bSAbel Vesa hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
48011f68120SShawn Guo
48111f68120SShawn Guo /* type name parent_name base div_mask */
482992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1", "osc", base + 0x00, 0x7f);
483992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
484992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3", "osc", base + 0x10, 0x3);
485992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll4", "osc", base + 0x70, 0x7f);
486992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5", "osc", base + 0xa0, 0x7f);
487992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3);
488992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll7", "osc", base + 0x20, 0x3);
48911f68120SShawn Guo
490992b703bSAbel Vesa hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
491992b703bSAbel Vesa hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
492992b703bSAbel Vesa hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
493992b703bSAbel Vesa hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
494992b703bSAbel Vesa hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
495992b703bSAbel Vesa hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
496992b703bSAbel Vesa hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
49711f68120SShawn Guo
49811f68120SShawn Guo /* Do not bypass PLLs initially */
499992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk);
500992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk);
501992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk);
502992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk);
503992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk);
504992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk);
505992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk);
50611f68120SShawn Guo
507992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL1_SYS] = imx_clk_hw_gate("pll1_sys", "pll1_bypass", base + 0x00, 13);
508992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_BUS] = imx_clk_hw_gate("pll2_bus", "pll2_bypass", base + 0x30, 13);
509992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_USB_OTG] = imx_clk_hw_gate("pll3_usb_otg", "pll3_bypass", base + 0x10, 13);
510992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL4_AUDIO] = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
511992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL5_VIDEO] = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
512992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL6_ENET] = imx_clk_hw_gate("pll6_enet", "pll6_bypass", base + 0xe0, 13);
513992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
51411f68120SShawn Guo
51511f68120SShawn Guo /*
51611f68120SShawn Guo * Bit 20 is the reserved and read-only bit, we do this only for:
51711f68120SShawn Guo * - Do nothing for usbphy clk_enable/disable
51811f68120SShawn Guo * - Keep refcount when do usbphy clk_enable/disable, in that case,
51911f68120SShawn Guo * the clk framework may need to enable/disable usbphy's parent
52011f68120SShawn Guo */
521992b703bSAbel Vesa hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
522992b703bSAbel Vesa hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
52311f68120SShawn Guo
52411f68120SShawn Guo /*
52511f68120SShawn Guo * usbphy*_gate needs to be on after system boots up, and software
52611f68120SShawn Guo * never needs to control it anymore.
52711f68120SShawn Guo */
528992b703bSAbel Vesa hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
529992b703bSAbel Vesa hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
53011f68120SShawn Guo
5313cc48976SLucas Stach /*
5323cc48976SLucas Stach * The ENET PLL is special in that is has multiple outputs with
5333cc48976SLucas Stach * different post-dividers that are all affected by the single bypass
5343cc48976SLucas Stach * bit, so a single mux bit affects 3 independent branches of the clock
5353cc48976SLucas Stach * tree. There is no good way to model this in the clock framework and
5363cc48976SLucas Stach * dynamically changing the bypass bit, will yield unexpected results.
5373cc48976SLucas Stach * So we treat any configuration that bypasses the ENET PLL as
5383cc48976SLucas Stach * essentially static with the divider ratios reflecting the bypass
5393cc48976SLucas Stach * status.
5403cc48976SLucas Stach *
5413cc48976SLucas Stach */
5423cc48976SLucas Stach if (!pll6_bypassed(ccm_node)) {
543992b703bSAbel Vesa hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 5);
544992b703bSAbel Vesa hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
545992b703bSAbel Vesa hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
54611f68120SShawn Guo base + 0xe0, 0, 2, 0, clk_enet_ref_table,
54711f68120SShawn Guo &imx_ccm_lock);
5483cc48976SLucas Stach } else {
549992b703bSAbel Vesa hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 1);
550992b703bSAbel Vesa hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 1);
551992b703bSAbel Vesa hws[IMX6QDL_CLK_ENET_REF] = imx_clk_hw_fixed_factor("enet_ref", "pll6_enet", 1, 1);
5523cc48976SLucas Stach }
5533cc48976SLucas Stach
554992b703bSAbel Vesa hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
555992b703bSAbel Vesa hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
55611f68120SShawn Guo
557992b703bSAbel Vesa hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
558992b703bSAbel Vesa hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
55911f68120SShawn Guo
56011f68120SShawn Guo /*
56111f68120SShawn Guo * lvds1_gate and lvds2_gate are pseudo-gates. Both can be
56211f68120SShawn Guo * independently configured as clock inputs or outputs. We treat
56311f68120SShawn Guo * the "output_enable" bit as a gate, even though it's really just
564f7542d81SLucas Stach * enabling clock output. Initially the gate bits are cleared, as
565f7542d81SLucas Stach * otherwise the exclusive configuration gets locked in the setup done
566f7542d81SLucas Stach * by software running before the clock driver, with no way to change
567f7542d81SLucas Stach * it.
56811f68120SShawn Guo */
569f7542d81SLucas Stach writel(readl(base + 0x160) & ~0x3c00, base + 0x160);
570992b703bSAbel Vesa hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
571992b703bSAbel Vesa hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
57211f68120SShawn Guo
573992b703bSAbel Vesa hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
574992b703bSAbel Vesa hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
57511f68120SShawn Guo
57611f68120SShawn Guo /* name parent_name reg idx */
577992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
578992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
579992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2);
580992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0, 0);
581992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0, 1);
582992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0, 2);
583992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0, 3);
58411f68120SShawn Guo
58511f68120SShawn Guo /* name parent_name mult div */
586992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
587992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg", 1, 4);
588992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
589992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_60M] = imx_clk_hw_fixed_factor("pll3_60m", "pll3_usb_otg", 1, 8);
590992b703bSAbel Vesa hws[IMX6QDL_CLK_TWD] = imx_clk_hw_fixed_factor("twd", "arm", 1, 2);
591992b703bSAbel Vesa hws[IMX6QDL_CLK_GPT_3M] = imx_clk_hw_fixed_factor("gpt_3m", "osc", 1, 8);
592992b703bSAbel Vesa hws[IMX6QDL_CLK_VIDEO_27M] = imx_clk_hw_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
593ee360274SBai Ping if (clk_on_imx6dl() || clk_on_imx6qp()) {
594992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
595992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
59611f68120SShawn Guo }
59711f68120SShawn Guo
598992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
5993ff86050SJan Remmet if (clk_on_imx6q() || clk_on_imx6qp())
6003ff86050SJan Remmet hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = imx_clk_hw_fixed_factor("pll4_audio_div", "pll4_post_div", 1, 1);
6013ff86050SJan Remmet else
602992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
603992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
604992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
60511f68120SShawn Guo
60611f68120SShawn Guo np = ccm_node;
60711f68120SShawn Guo base = of_iomap(np, 0);
60811f68120SShawn Guo WARN_ON(!base);
60911f68120SShawn Guo
61011f68120SShawn Guo /* name reg shift width parent_names num_parents */
611992b703bSAbel Vesa hws[IMX6QDL_CLK_STEP] = imx_clk_hw_mux("step", base + 0xc, 8, 1, step_sels, ARRAY_SIZE(step_sels));
612992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL1_SW] = imx_clk_hw_mux("pll1_sw", base + 0xc, 2, 1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels));
613992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH_PRE] = imx_clk_hw_mux("periph_pre", base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
614992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH2_PRE] = imx_clk_hw_mux("periph2_pre", base + 0x18, 21, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
615992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH_CLK2_SEL] = imx_clk_hw_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
616992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
617992b703bSAbel Vesa hws[IMX6QDL_CLK_AXI_SEL] = imx_clk_hw_mux("axi_sel", base + 0x14, 6, 2, axi_sels, ARRAY_SIZE(axi_sels));
618992b703bSAbel Vesa hws[IMX6QDL_CLK_ESAI_SEL] = imx_clk_hw_mux("esai_sel", base + 0x20, 19, 2, audio_sels, ARRAY_SIZE(audio_sels));
619992b703bSAbel Vesa hws[IMX6QDL_CLK_ASRC_SEL] = imx_clk_hw_mux("asrc_sel", base + 0x30, 7, 2, audio_sels, ARRAY_SIZE(audio_sels));
620992b703bSAbel Vesa hws[IMX6QDL_CLK_SPDIF_SEL] = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, audio_sels, ARRAY_SIZE(audio_sels));
62111f68120SShawn Guo if (clk_on_imx6q()) {
622992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_mux("gpu2d_axi", base + 0x18, 0, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
623992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_mux("gpu3d_axi", base + 0x18, 1, 1, gpu_axi_sels, ARRAY_SIZE(gpu_axi_sels));
62411f68120SShawn Guo }
625ee360274SBai Ping if (clk_on_imx6qp()) {
626992b703bSAbel Vesa hws[IMX6QDL_CLK_CAN_SEL] = imx_clk_hw_mux("can_sel", base + 0x20, 8, 2, can_sels, ARRAY_SIZE(can_sels));
627992b703bSAbel Vesa hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
628992b703bSAbel Vesa hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels));
629992b703bSAbel Vesa hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
630992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2));
631b1d51b44SLucas Stach } else if (clk_on_imx6dl()) {
632992b703bSAbel Vesa hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
633ee360274SBai Ping } else {
634992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels, ARRAY_SIZE(gpu2d_core_sels));
635ee360274SBai Ping }
636992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU3D_CORE_SEL] = imx_clk_hw_mux("gpu3d_core_sel", base + 0x18, 4, 2, gpu3d_core_sels, ARRAY_SIZE(gpu3d_core_sels));
637b1d51b44SLucas Stach if (clk_on_imx6dl())
638992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
639b1d51b44SLucas Stach else
640992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel", base + 0x18, 8, 2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
641992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_SEL] = imx_clk_hw_mux("ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
642992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_SEL] = imx_clk_hw_mux("ipu2_sel", base + 0x3c, 14, 2, ipu_sels, ARRAY_SIZE(ipu_sels));
6435d283b08SFabio Estevam
6445d283b08SFabio Estevam disable_anatop_clocks(anatop_base);
6455d283b08SFabio Estevam
646c129b6feSAnson Huang imx_mmdc_mask_handshake(base, 1);
6475d283b08SFabio Estevam
648f4a0a6c3SLucas Stach if (clk_on_imx6qp()) {
649992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
650992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
651f4a0a6c3SLucas Stach } else {
6525d283b08SFabio Estevam /*
6535d283b08SFabio Estevam * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
6545d283b08SFabio Estevam * bug. Set the muxes to the requested values before registering the
6555d283b08SFabio Estevam * ldb_di_sel clocks.
6565d283b08SFabio Estevam */
6575d283b08SFabio Estevam init_ldb_clks(np, base);
6585d283b08SFabio Estevam
659992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI0_SEL] = imx_clk_hw_mux_ldb("ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
660992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI1_SEL] = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels));
661f4a0a6c3SLucas Stach }
662992b703bSAbel Vesa
663992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
664992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
665992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
666992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels, ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
667992b703bSAbel Vesa hws[IMX6QDL_CLK_HSI_TX_SEL] = imx_clk_hw_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
668992b703bSAbel Vesa hws[IMX6QDL_CLK_PCIE_AXI_SEL] = imx_clk_hw_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
669992b703bSAbel Vesa
670ee360274SBai Ping if (clk_on_imx6qp()) {
671992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels_2, ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT);
672992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels_2, ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT);
673992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels_2, ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT);
674992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels_2, ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT);
675992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
676992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
677992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels));
678992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
679992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
680992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
681992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
682992b703bSAbel Vesa hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 15, 3, enfc_sels_2, ARRAY_SIZE(enfc_sels_2));
683992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels));
684992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
685992b703bSAbel Vesa hws[IMX6QDL_CLK_PRE_AXI] = imx_clk_hw_mux("pre_axi", base + 0x18, 1, 1, pre_axi_sels, ARRAY_SIZE(pre_axi_sels));
686ee360274SBai Ping } else {
687992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI0_SEL] = imx_clk_hw_mux_flags("ipu1_di0_sel", base + 0x34, 0, 3, ipu1_di0_sels, ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
688992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI1_SEL] = imx_clk_hw_mux_flags("ipu1_di1_sel", base + 0x34, 9, 3, ipu1_di1_sels, ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
689992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI0_SEL] = imx_clk_hw_mux_flags("ipu2_di0_sel", base + 0x38, 0, 3, ipu2_di0_sels, ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
690992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI1_SEL] = imx_clk_hw_mux_flags("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
691992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI1_SEL] = imx_clk_hw_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
692992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI2_SEL] = imx_clk_hw_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
693992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI3_SEL] = imx_clk_hw_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
694992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC1_SEL] = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
695992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC2_SEL] = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
696992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC3_SEL] = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
697992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC4_SEL] = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
698992b703bSAbel Vesa hws[IMX6QDL_CLK_ENFC_SEL] = imx_clk_hw_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
699992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_SEL] = imx_clk_hw_fixup_mux("eim_sel", base + 0x1c, 27, 2, eim_sels, ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
700992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_SLOW_SEL] = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
701ee360274SBai Ping }
702992b703bSAbel Vesa
703992b703bSAbel Vesa hws[IMX6QDL_CLK_VDO_AXI_SEL] = imx_clk_hw_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
704992b703bSAbel Vesa hws[IMX6QDL_CLK_VPU_AXI_SEL] = imx_clk_hw_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
705992b703bSAbel Vesa hws[IMX6QDL_CLK_CKO1_SEL] = imx_clk_hw_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
706992b703bSAbel Vesa hws[IMX6QDL_CLK_CKO2_SEL] = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
707992b703bSAbel Vesa hws[IMX6QDL_CLK_CKO] = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
70811f68120SShawn Guo
70911f68120SShawn Guo /* name reg shift width busy: reg, shift parent_names num_parents */
710992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH] = imx_clk_hw_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
711992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
71211f68120SShawn Guo
71311f68120SShawn Guo /* name parent_name reg shift width */
714992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
715992b703bSAbel Vesa hws[IMX6QDL_CLK_PERIPH2_CLK2] = imx_clk_hw_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
716992b703bSAbel Vesa hws[IMX6QDL_CLK_IPG] = imx_clk_hw_divider("ipg", "ahb", base + 0x14, 8, 2);
717992b703bSAbel Vesa hws[IMX6QDL_CLK_ESAI_PRED] = imx_clk_hw_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
718992b703bSAbel Vesa hws[IMX6QDL_CLK_ESAI_PODF] = imx_clk_hw_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
719992b703bSAbel Vesa hws[IMX6QDL_CLK_ASRC_PRED] = imx_clk_hw_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
720992b703bSAbel Vesa hws[IMX6QDL_CLK_ASRC_PODF] = imx_clk_hw_divider("asrc_podf", "asrc_pred", base + 0x30, 9, 3);
721992b703bSAbel Vesa hws[IMX6QDL_CLK_SPDIF_PRED] = imx_clk_hw_divider("spdif_pred", "spdif_sel", base + 0x30, 25, 3);
722992b703bSAbel Vesa hws[IMX6QDL_CLK_SPDIF_PODF] = imx_clk_hw_divider("spdif_podf", "spdif_pred", base + 0x30, 22, 3);
723992b703bSAbel Vesa
724ee360274SBai Ping if (clk_on_imx6qp()) {
725992b703bSAbel Vesa hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6);
726992b703bSAbel Vesa hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
727992b703bSAbel Vesa hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "can_sel", base + 0x20, 2, 6);
728992b703bSAbel Vesa hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6);
729992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7);
730992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
731ee360274SBai Ping } else {
732992b703bSAbel Vesa hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
733992b703bSAbel Vesa hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
734992b703bSAbel Vesa hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
735992b703bSAbel Vesa hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m", base + 0x24, 0, 6);
736992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
737992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
738ee360274SBai Ping }
739992b703bSAbel Vesa
740b1d51b44SLucas Stach if (clk_on_imx6dl())
741992b703bSAbel Vesa hws[IMX6QDL_CLK_MLB_PODF] = imx_clk_hw_divider("mlb_podf", "mlb_sel", base + 0x18, 23, 3);
742b1d51b44SLucas Stach else
743992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 23, 3);
744992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU3D_CORE_PODF] = imx_clk_hw_divider("gpu3d_core_podf", "gpu3d_core_sel", base + 0x18, 26, 3);
745b1d51b44SLucas Stach if (clk_on_imx6dl())
746992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_CORE_PODF] = imx_clk_hw_divider("gpu2d_core_podf", "gpu2d_core_sel", base + 0x18, 29, 3);
747b1d51b44SLucas Stach else
748992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU3D_SHADER] = imx_clk_hw_divider("gpu3d_shader", "gpu3d_shader_sel", base + 0x18, 29, 3);
749992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_PODF] = imx_clk_hw_divider("ipu1_podf", "ipu1_sel", base + 0x3c, 11, 3);
750992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_PODF] = imx_clk_hw_divider("ipu2_podf", "ipu2_sel", base + 0x3c, 16, 3);
751992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI0_PODF] = imx_clk_hw_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
752992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI1_PODF] = imx_clk_hw_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
753992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI0_PRE] = imx_clk_hw_divider("ipu1_di0_pre", "ipu1_di0_pre_sel", base + 0x34, 3, 3);
754992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI1_PRE] = imx_clk_hw_divider("ipu1_di1_pre", "ipu1_di1_pre_sel", base + 0x34, 12, 3);
755992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI0_PRE] = imx_clk_hw_divider("ipu2_di0_pre", "ipu2_di0_pre_sel", base + 0x38, 3, 3);
756992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI1_PRE] = imx_clk_hw_divider("ipu2_di1_pre", "ipu2_di1_pre_sel", base + 0x38, 12, 3);
757992b703bSAbel Vesa hws[IMX6QDL_CLK_HSI_TX_PODF] = imx_clk_hw_divider("hsi_tx_podf", "hsi_tx_sel", base + 0x30, 29, 3);
758992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI1_PRED] = imx_clk_hw_divider("ssi1_pred", "ssi1_sel", base + 0x28, 6, 3);
759992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI1_PODF] = imx_clk_hw_divider("ssi1_podf", "ssi1_pred", base + 0x28, 0, 6);
760992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI2_PRED] = imx_clk_hw_divider("ssi2_pred", "ssi2_sel", base + 0x2c, 6, 3);
761992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI2_PODF] = imx_clk_hw_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
762992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI3_PRED] = imx_clk_hw_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
763992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI3_PODF] = imx_clk_hw_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
764992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3);
765992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", base + 0x24, 16, 3);
766992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC3_PODF] = imx_clk_hw_divider("usdhc3_podf", "usdhc3_sel", base + 0x24, 19, 3);
767992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC4_PODF] = imx_clk_hw_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
768992b703bSAbel Vesa hws[IMX6QDL_CLK_ENFC_PRED] = imx_clk_hw_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
769992b703bSAbel Vesa hws[IMX6QDL_CLK_ENFC_PODF] = imx_clk_hw_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
770ee360274SBai Ping if (clk_on_imx6qp()) {
771992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3);
772992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3);
773ee360274SBai Ping } else {
774992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_PODF] = imx_clk_hw_fixup_divider("eim_podf", "eim_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
775992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_SLOW_PODF] = imx_clk_hw_fixup_divider("eim_slow_podf", "eim_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
776ee360274SBai Ping }
777992b703bSAbel Vesa
778992b703bSAbel Vesa hws[IMX6QDL_CLK_VPU_AXI_PODF] = imx_clk_hw_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
779992b703bSAbel Vesa hws[IMX6QDL_CLK_CKO1_PODF] = imx_clk_hw_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
780992b703bSAbel Vesa hws[IMX6QDL_CLK_CKO2_PODF] = imx_clk_hw_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
78111f68120SShawn Guo
78211f68120SShawn Guo /* name parent_name reg shift width busy: reg, shift */
783992b703bSAbel Vesa hws[IMX6QDL_CLK_AXI] = imx_clk_hw_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
784992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch0_axi_podf", "periph", base + 0x14, 19, 3, base + 0x48, 4);
785ee360274SBai Ping if (clk_on_imx6qp()) {
786992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18);
787992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2);
788ee360274SBai Ping } else {
789992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "periph2", base + 0x14, 3, 3, base + 0x48, 2);
790ee360274SBai Ping }
791992b703bSAbel Vesa hws[IMX6QDL_CLK_ARM] = imx_clk_hw_busy_divider("arm", "pll1_sw", base + 0x10, 0, 3, base + 0x48, 16);
792992b703bSAbel Vesa hws[IMX6QDL_CLK_AHB] = imx_clk_hw_busy_divider("ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1);
79311f68120SShawn Guo
79411f68120SShawn Guo /* name parent_name reg shift */
795992b703bSAbel Vesa hws[IMX6QDL_CLK_APBH_DMA] = imx_clk_hw_gate2("apbh_dma", "usdhc3", base + 0x68, 4);
796992b703bSAbel Vesa hws[IMX6QDL_CLK_ASRC] = imx_clk_hw_gate2_shared("asrc", "asrc_podf", base + 0x68, 6, &share_count_asrc);
797992b703bSAbel Vesa hws[IMX6QDL_CLK_ASRC_IPG] = imx_clk_hw_gate2_shared("asrc_ipg", "ahb", base + 0x68, 6, &share_count_asrc);
798992b703bSAbel Vesa hws[IMX6QDL_CLK_ASRC_MEM] = imx_clk_hw_gate2_shared("asrc_mem", "ahb", base + 0x68, 6, &share_count_asrc);
799992b703bSAbel Vesa hws[IMX6QDL_CLK_CAAM_MEM] = imx_clk_hw_gate2("caam_mem", "ahb", base + 0x68, 8);
800992b703bSAbel Vesa hws[IMX6QDL_CLK_CAAM_ACLK] = imx_clk_hw_gate2("caam_aclk", "ahb", base + 0x68, 10);
801992b703bSAbel Vesa hws[IMX6QDL_CLK_CAAM_IPG] = imx_clk_hw_gate2("caam_ipg", "ipg", base + 0x68, 12);
802992b703bSAbel Vesa hws[IMX6QDL_CLK_CAN1_IPG] = imx_clk_hw_gate2("can1_ipg", "ipg", base + 0x68, 14);
803992b703bSAbel Vesa hws[IMX6QDL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial", "can_root", base + 0x68, 16);
804992b703bSAbel Vesa hws[IMX6QDL_CLK_CAN2_IPG] = imx_clk_hw_gate2("can2_ipg", "ipg", base + 0x68, 18);
805992b703bSAbel Vesa hws[IMX6QDL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial", "can_root", base + 0x68, 20);
806992b703bSAbel Vesa hws[IMX6QDL_CLK_DCIC1] = imx_clk_hw_gate2("dcic1", "ipu1_podf", base + 0x68, 24);
807992b703bSAbel Vesa hws[IMX6QDL_CLK_DCIC2] = imx_clk_hw_gate2("dcic2", "ipu2_podf", base + 0x68, 26);
808992b703bSAbel Vesa hws[IMX6QDL_CLK_ECSPI1] = imx_clk_hw_gate2("ecspi1", "ecspi_root", base + 0x6c, 0);
809992b703bSAbel Vesa hws[IMX6QDL_CLK_ECSPI2] = imx_clk_hw_gate2("ecspi2", "ecspi_root", base + 0x6c, 2);
810992b703bSAbel Vesa hws[IMX6QDL_CLK_ECSPI3] = imx_clk_hw_gate2("ecspi3", "ecspi_root", base + 0x6c, 4);
811992b703bSAbel Vesa hws[IMX6QDL_CLK_ECSPI4] = imx_clk_hw_gate2("ecspi4", "ecspi_root", base + 0x6c, 6);
81211f68120SShawn Guo if (clk_on_imx6dl())
813992b703bSAbel Vesa hws[IMX6DL_CLK_I2C4] = imx_clk_hw_gate2("i2c4", "ipg_per", base + 0x6c, 8);
81411f68120SShawn Guo else
815992b703bSAbel Vesa hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5", "ecspi_root", base + 0x6c, 8);
816992b703bSAbel Vesa hws[IMX6QDL_CLK_ENET] = imx_clk_hw_gate2("enet", "ipg", base + 0x6c, 10);
817992b703bSAbel Vesa hws[IMX6QDL_CLK_EPIT1] = imx_clk_hw_gate2("epit1", "ipg", base + 0x6c, 12);
818992b703bSAbel Vesa hws[IMX6QDL_CLK_EPIT2] = imx_clk_hw_gate2("epit2", "ipg", base + 0x6c, 14);
819992b703bSAbel Vesa hws[IMX6QDL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf", base + 0x6c, 16, &share_count_esai);
820992b703bSAbel Vesa hws[IMX6QDL_CLK_ESAI_IPG] = imx_clk_hw_gate2_shared("esai_ipg", "ahb", base + 0x6c, 16, &share_count_esai);
821992b703bSAbel Vesa hws[IMX6QDL_CLK_ESAI_MEM] = imx_clk_hw_gate2_shared("esai_mem", "ahb", base + 0x6c, 16, &share_count_esai);
822992b703bSAbel Vesa hws[IMX6QDL_CLK_GPT_IPG] = imx_clk_hw_gate2("gpt_ipg", "ipg", base + 0x6c, 20);
823992b703bSAbel Vesa hws[IMX6QDL_CLK_GPT_IPG_PER] = imx_clk_hw_gate2("gpt_ipg_per", "ipg_per", base + 0x6c, 22);
824992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
825992b703bSAbel Vesa hws[IMX6QDL_CLK_GPU3D_CORE] = imx_clk_hw_gate2("gpu3d_core", "gpu3d_core_podf", base + 0x6c, 26);
826992b703bSAbel Vesa hws[IMX6QDL_CLK_HDMI_IAHB] = imx_clk_hw_gate2("hdmi_iahb", "ahb", base + 0x70, 0);
827992b703bSAbel Vesa hws[IMX6QDL_CLK_HDMI_ISFR] = imx_clk_hw_gate2("hdmi_isfr", "mipi_core_cfg", base + 0x70, 4);
828992b703bSAbel Vesa hws[IMX6QDL_CLK_I2C1] = imx_clk_hw_gate2("i2c1", "ipg_per", base + 0x70, 6);
829992b703bSAbel Vesa hws[IMX6QDL_CLK_I2C2] = imx_clk_hw_gate2("i2c2", "ipg_per", base + 0x70, 8);
830992b703bSAbel Vesa hws[IMX6QDL_CLK_I2C3] = imx_clk_hw_gate2("i2c3", "ipg_per", base + 0x70, 10);
831992b703bSAbel Vesa hws[IMX6QDL_CLK_IIM] = imx_clk_hw_gate2("iim", "ipg", base + 0x70, 12);
832992b703bSAbel Vesa hws[IMX6QDL_CLK_ENFC] = imx_clk_hw_gate2("enfc", "enfc_podf", base + 0x70, 14);
833992b703bSAbel Vesa hws[IMX6QDL_CLK_VDOA] = imx_clk_hw_gate2("vdoa", "vdo_axi", base + 0x70, 26);
834992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1] = imx_clk_hw_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
835992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI0] = imx_clk_hw_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
836992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU1_DI1] = imx_clk_hw_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
837992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2] = imx_clk_hw_gate2("ipu2", "ipu2_podf", base + 0x74, 6);
838992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI0] = imx_clk_hw_gate2("ipu2_di0", "ipu2_di0_sel", base + 0x74, 8);
839ee360274SBai Ping if (clk_on_imx6qp()) {
840992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_sel", base + 0x74, 12);
841992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_sel", base + 0x74, 14);
842ee360274SBai Ping } else {
843992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI0] = imx_clk_hw_gate2("ldb_di0", "ldb_di0_podf", base + 0x74, 12);
844992b703bSAbel Vesa hws[IMX6QDL_CLK_LDB_DI1] = imx_clk_hw_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
845ee360274SBai Ping }
846992b703bSAbel Vesa hws[IMX6QDL_CLK_IPU2_DI1] = imx_clk_hw_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
847992b703bSAbel Vesa hws[IMX6QDL_CLK_HSI_TX] = imx_clk_hw_gate2_shared("hsi_tx", "hsi_tx_podf", base + 0x74, 16, &share_count_mipi_core_cfg);
848992b703bSAbel Vesa hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
849992b703bSAbel Vesa hws[IMX6QDL_CLK_MIPI_IPG] = imx_clk_hw_gate2_shared("mipi_ipg", "ipg", base + 0x74, 16, &share_count_mipi_core_cfg);
850992b703bSAbel Vesa
85111f68120SShawn Guo if (clk_on_imx6dl())
85211f68120SShawn Guo /*
85311f68120SShawn Guo * The multiplexer and divider of the imx6q clock gpu2d get
85411f68120SShawn Guo * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
85511f68120SShawn Guo */
856992b703bSAbel Vesa hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "mlb_podf", base + 0x74, 18);
85711f68120SShawn Guo else
858992b703bSAbel Vesa hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb", "axi", base + 0x74, 18);
859992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL);
860992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
861992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg", base + 0x74, 24, CLK_IS_CRITICAL);
862992b703bSAbel Vesa hws[IMX6QDL_CLK_OCRAM] = imx_clk_hw_gate2("ocram", "ahb", base + 0x74, 28);
863992b703bSAbel Vesa hws[IMX6QDL_CLK_OPENVG_AXI] = imx_clk_hw_gate2("openvg_axi", "axi", base + 0x74, 30);
864992b703bSAbel Vesa hws[IMX6QDL_CLK_PCIE_AXI] = imx_clk_hw_gate2("pcie_axi", "pcie_axi_sel", base + 0x78, 0);
865992b703bSAbel Vesa hws[IMX6QDL_CLK_PER1_BCH] = imx_clk_hw_gate2("per1_bch", "usdhc3", base + 0x78, 12);
866992b703bSAbel Vesa hws[IMX6QDL_CLK_PWM1] = imx_clk_hw_gate2("pwm1", "ipg_per", base + 0x78, 16);
867992b703bSAbel Vesa hws[IMX6QDL_CLK_PWM2] = imx_clk_hw_gate2("pwm2", "ipg_per", base + 0x78, 18);
868992b703bSAbel Vesa hws[IMX6QDL_CLK_PWM3] = imx_clk_hw_gate2("pwm3", "ipg_per", base + 0x78, 20);
869992b703bSAbel Vesa hws[IMX6QDL_CLK_PWM4] = imx_clk_hw_gate2("pwm4", "ipg_per", base + 0x78, 22);
870992b703bSAbel Vesa hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb", "usdhc3", base + 0x78, 24);
871992b703bSAbel Vesa hws[IMX6QDL_CLK_GPMI_BCH] = imx_clk_hw_gate2("gpmi_bch", "usdhc4", base + 0x78, 26);
872992b703bSAbel Vesa hws[IMX6QDL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io", "enfc", base + 0x78, 28);
873992b703bSAbel Vesa hws[IMX6QDL_CLK_GPMI_APB] = imx_clk_hw_gate2("gpmi_apb", "usdhc3", base + 0x78, 30);
874992b703bSAbel Vesa hws[IMX6QDL_CLK_ROM] = imx_clk_hw_gate2_flags("rom", "ahb", base + 0x7c, 0, CLK_IS_CRITICAL);
875992b703bSAbel Vesa hws[IMX6QDL_CLK_SATA] = imx_clk_hw_gate2("sata", "ahb", base + 0x7c, 4);
876992b703bSAbel Vesa hws[IMX6QDL_CLK_SDMA] = imx_clk_hw_gate2("sdma", "ahb", base + 0x7c, 6);
877992b703bSAbel Vesa hws[IMX6QDL_CLK_SPBA] = imx_clk_hw_gate2("spba", "ipg", base + 0x7c, 12);
878992b703bSAbel Vesa hws[IMX6QDL_CLK_SPDIF] = imx_clk_hw_gate2_shared("spdif", "spdif_podf", base + 0x7c, 14, &share_count_spdif);
879992b703bSAbel Vesa hws[IMX6QDL_CLK_SPDIF_GCLK] = imx_clk_hw_gate2_shared("spdif_gclk", "ipg", base + 0x7c, 14, &share_count_spdif);
880992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI1_IPG] = imx_clk_hw_gate2_shared("ssi1_ipg", "ipg", base + 0x7c, 18, &share_count_ssi1);
881992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI2_IPG] = imx_clk_hw_gate2_shared("ssi2_ipg", "ipg", base + 0x7c, 20, &share_count_ssi2);
882992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI3_IPG] = imx_clk_hw_gate2_shared("ssi3_ipg", "ipg", base + 0x7c, 22, &share_count_ssi3);
883992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI1] = imx_clk_hw_gate2_shared("ssi1", "ssi1_podf", base + 0x7c, 18, &share_count_ssi1);
884992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI2] = imx_clk_hw_gate2_shared("ssi2", "ssi2_podf", base + 0x7c, 20, &share_count_ssi2);
885992b703bSAbel Vesa hws[IMX6QDL_CLK_SSI3] = imx_clk_hw_gate2_shared("ssi3", "ssi3_podf", base + 0x7c, 22, &share_count_ssi3);
886992b703bSAbel Vesa hws[IMX6QDL_CLK_UART_IPG] = imx_clk_hw_gate2("uart_ipg", "ipg", base + 0x7c, 24);
887992b703bSAbel Vesa hws[IMX6QDL_CLK_UART_SERIAL] = imx_clk_hw_gate2("uart_serial", "uart_serial_podf", base + 0x7c, 26);
888992b703bSAbel Vesa hws[IMX6QDL_CLK_USBOH3] = imx_clk_hw_gate2("usboh3", "ipg", base + 0x80, 0);
889992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", base + 0x80, 2);
890992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", base + 0x80, 4);
891992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC3] = imx_clk_hw_gate2("usdhc3", "usdhc3_podf", base + 0x80, 6);
892992b703bSAbel Vesa hws[IMX6QDL_CLK_USDHC4] = imx_clk_hw_gate2("usdhc4", "usdhc4_podf", base + 0x80, 8);
893992b703bSAbel Vesa hws[IMX6QDL_CLK_EIM_SLOW] = imx_clk_hw_gate2("eim_slow", "eim_slow_podf", base + 0x80, 10);
894992b703bSAbel Vesa hws[IMX6QDL_CLK_VDO_AXI] = imx_clk_hw_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
895992b703bSAbel Vesa hws[IMX6QDL_CLK_VPU_AXI] = imx_clk_hw_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
896ee360274SBai Ping if (clk_on_imx6qp()) {
897992b703bSAbel Vesa hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0", "pre_axi", base + 0x80, 16);
898992b703bSAbel Vesa hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1", "pre_axi", base + 0x80, 18);
899992b703bSAbel Vesa hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2", "pre_axi", base + 0x80, 20);
900992b703bSAbel Vesa hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3", "pre_axi", base + 0x80, 22);
901992b703bSAbel Vesa hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi", "ipu1_podf", base + 0x80, 24, &share_count_prg0);
902992b703bSAbel Vesa hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi", "ipu2_podf", base + 0x80, 26, &share_count_prg1);
903992b703bSAbel Vesa hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb", "ipg", base + 0x80, 24, &share_count_prg0);
904992b703bSAbel Vesa hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb", "ipg", base + 0x80, 26, &share_count_prg1);
905ee360274SBai Ping }
906992b703bSAbel Vesa hws[IMX6QDL_CLK_CKO1] = imx_clk_hw_gate("cko1", "cko1_podf", base + 0x60, 7);
907992b703bSAbel Vesa hws[IMX6QDL_CLK_CKO2] = imx_clk_hw_gate("cko2", "cko2_podf", base + 0x60, 24);
90811f68120SShawn Guo
90911f68120SShawn Guo /*
91011f68120SShawn Guo * The gpt_3m clock is not available on i.MX6Q TO1.0. Let's point it
91111f68120SShawn Guo * to clock gpt_ipg_per to ease the gpt driver code.
91211f68120SShawn Guo */
91311f68120SShawn Guo if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
914992b703bSAbel Vesa hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER];
91511f68120SShawn Guo
916*8bb289bbSOleksij Rempel hws[IMX6QDL_CLK_ENET_REF_PAD] = imx6q_obtain_fixed_clk_hw(ccm_node, "enet_ref_pad", 0);
917*8bb289bbSOleksij Rempel
918*8bb289bbSOleksij Rempel hws[IMX6QDL_CLK_ENET_REF_SEL] = imx_clk_gpr_mux("enet_ref_sel", "fsl,imx6q-iomuxc-gpr",
919*8bb289bbSOleksij Rempel IOMUXC_GPR1, enet_ref_sels, ARRAY_SIZE(enet_ref_sels),
920*8bb289bbSOleksij Rempel enet_ref_sels_table, enet_ref_sels_table_mask);
921*8bb289bbSOleksij Rempel
922992b703bSAbel Vesa imx_check_clk_hws(hws, IMX6QDL_CLK_END);
92311f68120SShawn Guo
924992b703bSAbel Vesa of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
92511f68120SShawn Guo
926992b703bSAbel Vesa clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
92711f68120SShawn Guo
928992b703bSAbel Vesa clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000);
92905e062f9SFabio Estevam if (clk_on_imx6dl())
930992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk);
93105e062f9SFabio Estevam
932992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
933992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
934992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
935992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
936992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk);
937992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk);
938992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk);
939992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk);
94011f68120SShawn Guo
94111f68120SShawn Guo /*
94211f68120SShawn Guo * The gpmi needs 100MHz frequency in the EDO/Sync mode,
94311f68120SShawn Guo * We can not get the 100MHz from the pll2_pfd0_352m.
94411f68120SShawn Guo * So choose pll2_pfd2_396m as enfc_sel's parent.
94511f68120SShawn Guo */
946992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk);
94711f68120SShawn Guo
94811f68120SShawn Guo if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
949992b703bSAbel Vesa clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk);
950992b703bSAbel Vesa clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk);
95111f68120SShawn Guo }
95211f68120SShawn Guo
95311f68120SShawn Guo /*
95411f68120SShawn Guo * Let's initially set up CLKO with OSC24M, since this configuration
95511f68120SShawn Guo * is widely used by imx6q board designs to clock audio codec.
95611f68120SShawn Guo */
957992b703bSAbel Vesa ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk);
95811f68120SShawn Guo if (!ret)
959992b703bSAbel Vesa ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk);
96011f68120SShawn Guo if (ret)
96111f68120SShawn Guo pr_warn("failed to set up CLKO: %d\n", ret);
96211f68120SShawn Guo
96311f68120SShawn Guo /* Audio-related clocks configuration */
964992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk);
96511f68120SShawn Guo
96611f68120SShawn Guo /* All existing boards with PCIe use LVDS1 */
96711f68120SShawn Guo if (IS_ENABLED(CONFIG_PCI_IMX6))
968992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk);
9690822f933SLucas Stach
970d8846023SLucas Stach /*
971d8846023SLucas Stach * Initialize the GPU clock muxes, so that the maximum specified clock
972d8846023SLucas Stach * rates for the respective SoC are not exceeded.
973d8846023SLucas Stach */
974d8846023SLucas Stach if (clk_on_imx6dl()) {
975992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
976992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
977992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
978992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
979d8846023SLucas Stach } else if (clk_on_imx6q()) {
980992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
981992b703bSAbel Vesa hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk);
982992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk,
983992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
984992b703bSAbel Vesa clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
985992b703bSAbel Vesa hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
986992b703bSAbel Vesa }
987992b703bSAbel Vesa
988*8bb289bbSOleksij Rempel clk_set_parent(hws[IMX6QDL_CLK_ENET_REF_SEL]->clk, hws[IMX6QDL_CLK_ENET_REF]->clk);
989*8bb289bbSOleksij Rempel
9902d5513bfSPeng Fan imx_register_uart_clocks();
99111f68120SShawn Guo }
99211f68120SShawn Guo CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
993