Home
last modified time | relevance | path

Searched +full:secondary +full:- +full:boot +full:- +full:reg (Results 1 – 25 of 116) sorted by relevance

12345

/linux/arch/arm/boot/dts/broadcom/
H A Dbcm23550.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
8 #include "bcm2166x-common.dtsi"
11 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
20 reg = <0>;
21 clock-frequency = <1000000000>;
26 compatible = "arm,cortex-a7";
27 enable-method = "brcm,bcm23550";
[all …]
H A Dbcm-nsp-ax.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Broadcom Northstar Plus Ax stepping-specific bindings.
4 * Notable differences from B0+ are the secondary-boot-reg and
9 secondary-boot-reg = <0xffff042c>;
13 /delete-property/ dma-coherent;
17 /delete-property/ dma-coherent;
21 /delete-property/ dma-coherent;
25 /delete-property/ dma-coherent;
29 /delete-property/ dma-coherent;
33 /delete-property/ dma-coherent;
[all …]
H A Dbcm4708.dtsi5 * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
20 stdout-path = "serial0:115200n8";
24 #address-cells = <1>;
25 #size-cells = <0>;
26 enable-method = "brcm,bcm-nsp-smp";
30 compatible = "arm,cortex-a9";
31 next-level-cache = <&L2>;
32 reg = <0x0>;
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
[all …]
H A Dbcm21664.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
4 #include "bcm2166x-common.dtsi"
7 interrupt-parent = <&gic>;
10 #address-cells = <1>;
11 #size-cells = <0>;
15 compatible = "arm,cortex-a9";
16 reg = <0>;
21 compatible = "arm,cortex-a9";
22 enable-method = "brcm,bcm11351-cpu-method";
23 secondary-boot-reg = <0x35004178>;
[all …]
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
11 An optional Boot lookup table Device Tree node is required for secondary CPU
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
16 Required properties for the Boot lookup table node:
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
[all …]
/linux/arch/arm/mach-bcm/
H A Dplatsmp.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014-2015 Broadcom Corporation
12 #include <linux/irqchip/irq-bcm2836.h>
33 /* Name of device node property defining secondary boot register location */
34 #define OF_SECONDARY_BOOT "secondary-boot-reg"
54 return -ENXIO; in scu_a9_enable()
61 return -ENOENT; in scu_a9_enable()
68 return -ENOMEM; in scu_a9_enable()
91 pr_err("required secondary boot register not specified for CPU%u\n", in secondary_boot_addr_for()
106 return -EINVAL; in nsp_write_lut()
[all …]
/linux/arch/powerpc/boot/dts/
H A Dxpedite5301.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "PMC/XMC";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
28 #address-cells = <1>;
29 #size-cells = <0>;
33 reg = <0x0>;
34 d-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5330.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
[all …]
H A Dxpedite5370.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 reg = <0x0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxcalibur1501.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 * XCalibur1501 6U CompactPCI single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
27 #address-cells = <1>;
28 #size-cells = <0>;
32 reg = <0x0>;
33 d-cache-line-size = <32>; // 32 bytes
34 i-cache-line-size = <32>; // 32 bytes
[all …]
H A Dxpedite5200.dts1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
29 #address-cells = <1>;
30 #size-cells = <0>;
34 reg = <0>;
35 d-cache-line-size = <32>; // 32 bytes
36 i-cache-line-size = <32>; // 32 bytes
37 d-cache-size = <0x8000>; // L1, 32K
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
/linux/Documentation/devicetree/bindings/arm/mstar/
H A Dmstar,smpctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Daniel Palmer <daniel@thingy.jp>
15 have a region of registers that allow setting the boot address
16 and a magic number that allows secondary processors to leave
17 the loop they are parked in by the boot ROM.
22 - enum:
23 - sstar,ssd201-smpctrl # SSD201/SSD202D
24 - const: mstar,smpctrl
[all …]
/linux/Documentation/devicetree/bindings/openrisc/opencores/
H A Dor1ksim.txt6 specification, however some aspects, such as the boot protocol have been defined
10 -------------------
11 - compatible: Must include "opencores,or1ksim"
14 ----------
16 - #address-cells: Must be 1.
17 - #size-cells: Must be 0.
18 A CPU sub-node is also required for at least CPU 0. Since the topology may
19 be probed via CPS, it is not necessary to specify secondary CPUs. Required
21 - compatible: Must be "opencores,or1200-rtlsvn481".
22 - reg: CPU number.
[all …]
/linux/arch/arm64/kernel/
H A Dsmp.c1 // SPDX-License-Identifier: GPL-2.0-only
27 #include <linux/irqchip/arm-gic-v3.h>
60 * so we need some other way of telling a new secondary core
98 return -ENOSYS; in op_cpu_kill()
104 * Boot a secondary CPU, and assign it the specified idle task.
111 if (ops->cpu_boot) in boot_secondary()
112 return ops->cpu_boot(cpu); in boot_secondary()
114 return -EOPNOTSUPP; in boot_secondary()
125 * We need to tell the secondary core where to find its stack and the in __cpu_up()
134 if (ret != -EPERM) in __cpu_up()
[all …]
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * there's a little bit of over-abstraction that tends to obscure what's going
14 * user-visible instructions are available only on a subset of the available
16 * boot CPU and comparing these with the feature registers of each secondary
18 * snapshot state to indicate the lowest-common denominator of the feature,
31 * - Mismatched features are *always* sanitised to a "safe" value, which
34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK"
38 * - Features marked as FTR_VISIBLE have their sanitised value visible to
43 * - A "feature" is typically a 4-bit register field. A "capability" is the
44 * high-level description derived from the sanitised field value.
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
42 reg:
54 Bits [11:0] in the reg cell must be set to
57 All other bits in the reg cell must be set to 0.
[all …]
H A Dsyna.txt3 According to https://www.synaptics.com/company/news/conexant-marvell
7 ---------------------------------------------------------------
18 "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005)
20 "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114)
26 model = "Sony NSZ-GS7";
27 compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin";
38 - compatible: should be "marvell,berlin-cpu-ctrl"
39 - reg: address and length of the register set
43 cpu-ctrl@f7dd0000 {
44 compatible = "marvell,berlin-cpu-ctrl";
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhip01-ca9x2.dts1 // SPDX-License-Identifier: GPL-2.0-only
11 /dts-v1/;
13 /* First 8KB reserved for secondary core boot */
20 compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01";
23 #address-cells = <1>;
24 #size-cells = <0>;
25 enable-method = "hisilicon,hip01-smp";
29 compatible = "arm,cortex-a9";
30 reg = <0>;
35 compatible = "arm,cortex-a9";
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916-samsung-grandmax.dts1 // SPDX-License-Identifier: GPL-2.0-only
3 /dts-v1/;
5 #include "msm8916-samsung-e2015-common.dtsi"
6 #include <dt-bindings/leds/common.h>
9 * NOTE: The original firmware from Samsung can only boot ARM32 kernels on some
12 * There seems to be no way to boot ARM64 kernels on 32-bit devices at the
18 * arch/arm/boot/dts/qcom-msm8916-samsung-grandmax.dts
24 chassis-type = "handset";
26 /delete-node/ gpio-hall-sensor;
27 /delete-node/ i2c-nfc;
[all …]
H A Dmsm8994-sony-xperia-kitakami.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/gpio-keys.h>
18 * and requires driver-side changes (including CPR, be warned!!).
21 qcom,msm-id = <207 0x20000>, <207 0x20001>;
23 qcom,pmic-id = <0x10009 0x1000a 0x00 0x00>;
25 qcom,board-id = <8 0>;
28 /delete-node/ psci;
30 gpio-keys {
31 compatible = "gpio-keys";
[all …]
/linux/Documentation/devicetree/bindings/mips/img/
H A Dpistachio.txt5 --------------------
6 - compatible: Must include "img,pistachio".
9 ----------
11 - #address-cells: Must be 1.
12 - #size-cells: Must be 0.
13 A CPU sub-node is also required for at least CPU 0. Since the topology may
14 be probed via CPS, it is not necessary to specify secondary CPUs. Required
16 - device_type: Must be "cpu".
17 - compatible: Must be "mti,interaptiv".
18 - reg: CPU number.
[all …]
/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb-mp.dtsi23 #include <dt-bindings/interrupt-controller/irq.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "arm-realview-eb.dtsi"
30 * and Cortex-A9 MPCore.
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "arm,realview-eb-soc", "simple-bus";
41 intc: interrupt-controller@1f000100 {
42 compatible = "arm,eb11mp-gic";
43 #interrupt-cells = <3>;
[all …]
/linux/arch/arm/mach-exynos/
H A Dfirmware.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <asm/hardware/cache-l2x0.h>
61 * Exynos3250 doesn't need to send smc command for secondary CPU boot in exynos_cpu_boot()
72 * But, Exynos4212 has only one secondary CPU so second parameter in exynos_cpu_boot()
87 return -ENODEV; in exynos_set_cpu_boot_addr()
92 * Almost all Exynos-series of SoCs that run in secure mode don't need in exynos_set_cpu_boot_addr()
108 return -ENODEV; in exynos_get_cpu_boot_addr()
159 static void exynos_l2_write_sec(unsigned long val, unsigned reg) in exynos_l2_write_sec() argument
163 switch (reg) { in exynos_l2_write_sec()
185 WARN_ONCE(1, "%s: ignoring write to reg 0x%x\n", __func__, reg); in exynos_l2_write_sec()
[all …]
/linux/drivers/iio/imu/st_lsm6dsx/
H A Dst_lsm6dsx.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 #define ST_LSM6DS3TRC_DEV_NAME "lsm6ds3tr-c"
29 #define ST_LSM9DS1_DEV_NAME "lsm9ds1-imu"
138 struct st_lsm6dsx_reg reg; member
158 struct st_lsm6dsx_reg reg; member
165 * struct st_lsm6dsx_fifo_ops - ST IMU FIFO settings
189 * struct st_lsm6dsx_hw_ts_settings - ST IMU hw timer settings
205 * struct st_lsm6dsx_shub_settings - ST IMU hw i2c controller settings
208 * @pullup_en: i2c controller pull-up register info (addr + mask).
214 * @slv0_addr: slave0 address in secondary page.
[all …]

12345