Lines Matching +full:secondary +full:- +full:boot +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-only
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 form-factor = "3U CompactPCI";
16 boot-bank = <0x0>; /* 0: Primary flash, 1: Secondary flash */
29 #address-cells = <1>;
30 #size-cells = <0>;
33 cell-index = <0>;
37 * module-present;
43 #address-cells = <1>;
44 #size-cells = <0>;
47 cell-index = <0>;
50 * module-present;
58 * system-controller;
60 system-controller;
64 #address-cells = <1>;
65 #size-cells = <0>;
69 reg = <0x0>;
70 d-cache-line-size = <32>; // 32 bytes
71 i-cache-line-size = <32>; // 32 bytes
72 d-cache-size = <0x8000>; // L1, 32K
73 i-cache-size = <0x8000>; // L1, 32K
74 timebase-frequency = <0>;
75 bus-frequency = <0>;
76 clock-frequency = <0>;
77 next-level-cache = <&L2>;
82 reg = <0x1>;
83 d-cache-line-size = <32>; // 32 bytes
84 i-cache-line-size = <32>; // 32 bytes
85 d-cache-size = <0x8000>; // L1, 32K
86 i-cache-size = <0x8000>; // L1, 32K
87 timebase-frequency = <0>;
88 bus-frequency = <0>;
89 clock-frequency = <0>;
90 next-level-cache = <&L2>;
96 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
100 #address-cells = <2>;
101 #size-cells = <1>;
102 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
103 reg = <0 0xef005000 0 0x1000>;
105 interrupt-parent = <&mpic>;
107 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
112 nor-boot@0,0 {
113 compatible = "amd,s29gl01gp", "cfi-flash";
114 bank-width = <2>;
115 reg = <0 0 0x8000000>; /* 128MB */
116 #address-cells = <1>;
117 #size-cells = <1>;
120 reg = <0x00000000 0x6f00000>; /* 111 MB */
124 reg = <0x6f00000 0x1000000>; /* 16 MB */
128 reg = <0x7f00000 0x40000>; /* 256 KB */
131 label = "Primary U-Boot environment";
132 reg = <0x7f40000 0x40000>; /* 256 KB */
135 label = "Primary U-Boot";
136 reg = <0x7f80000 0x80000>; /* 512 KB */
137 read-only;
141 nor-alternate@1,0 {
142 compatible = "amd,s29gl01gp", "cfi-flash";
143 bank-width = <2>;
144 //reg = <0xf0000000 0x08000000>; /* 128MB */
145 reg = <1 0 0x8000000>; /* 128MB */
146 #address-cells = <1>;
147 #size-cells = <1>;
149 label = "Secondary user space";
150 reg = <0x00000000 0x6f00000>; /* 111 MB */
153 label = "Secondary kernel";
154 reg = <0x6f00000 0x1000000>; /* 16 MB */
157 label = "Secondary DTB";
158 reg = <0x7f00000 0x40000>; /* 256 KB */
161 label = "Secondary U-Boot environment";
162 reg = <0x7f40000 0x40000>; /* 256 KB */
165 label = "Secondary U-Boot";
166 reg = <0x7f80000 0x80000>; /* 512 KB */
167 read-only;
172 #address-cells = <1>;
173 #size-cells = <1>;
180 compatible = "fsl,mpc8572-fcm-nand",
181 "fsl,elbc-fcm-nand";
182 reg = <2 0 0x40000>;
183 /* U-Boot should fix this up if chip size > 1 GB */
186 reg = <0 0x40000000>;
193 #address-cells = <1>;
194 #size-cells = <1>;
196 compatible = "fsl,mpc8572-immr", "simple-bus";
198 bus-frequency = <0>; // Filled out by uboot.
200 ecm-law@0 {
201 compatible = "fsl,ecm-law";
202 reg = <0x0 0x1000>;
203 fsl,num-laws = <12>;
207 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
208 reg = <0x1000 0x1000>;
210 interrupt-parent = <&mpic>;
213 memory-controller@2000 {
214 compatible = "fsl,mpc8572-memory-controller";
215 reg = <0x2000 0x1000>;
216 interrupt-parent = <&mpic>;
220 memory-controller@6000 {
221 compatible = "fsl,mpc8572-memory-controller";
222 reg = <0x6000 0x1000>;
223 interrupt-parent = <&mpic>;
227 L2: l2-cache-controller@20000 {
228 compatible = "fsl,mpc8572-l2-cache-controller";
229 reg = <0x20000 0x1000>;
230 cache-line-size = <32>; // 32 bytes
231 cache-size = <0x100000>; // L2, 1M
232 interrupt-parent = <&mpic>;
237 #address-cells = <1>;
238 #size-cells = <0>;
239 cell-index = <0>;
240 compatible = "fsl-i2c";
241 reg = <0x3000 0x100>;
243 interrupt-parent = <&mpic>;
246 temp-sensor@48 {
248 reg = <0x48>;
251 temp-sensor@4c {
253 reg = <0x4c>;
256 cpu-supervisor@51 {
258 reg = <0x51>;
263 reg = <0x54>;
269 reg = <0x68>;
272 pcie-switch@70 {
274 reg = <0x70>;
279 reg = <0x18>;
280 #gpio-cells = <2>;
281 gpio-controller;
287 reg = <0x1c>;
288 #gpio-cells = <2>;
289 gpio-controller;
295 reg = <0x1e>;
296 #gpio-cells = <2>;
297 gpio-controller;
303 reg = <0x1f>;
304 #gpio-cells = <2>;
305 gpio-controller;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 cell-index = <1>;
314 compatible = "fsl-i2c";
315 reg = <0x3100 0x100>;
317 interrupt-parent = <&mpic>;
322 #address-cells = <1>;
323 #size-cells = <1>;
324 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
325 reg = <0xc300 0x4>;
327 cell-index = <1>;
328 dma-channel@0 {
329 compatible = "fsl,mpc8572-dma-channel",
330 "fsl,eloplus-dma-channel";
331 reg = <0x0 0x80>;
332 cell-index = <0>;
333 interrupt-parent = <&mpic>;
336 dma-channel@80 {
337 compatible = "fsl,mpc8572-dma-channel",
338 "fsl,eloplus-dma-channel";
339 reg = <0x80 0x80>;
340 cell-index = <1>;
341 interrupt-parent = <&mpic>;
344 dma-channel@100 {
345 compatible = "fsl,mpc8572-dma-channel",
346 "fsl,eloplus-dma-channel";
347 reg = <0x100 0x80>;
348 cell-index = <2>;
349 interrupt-parent = <&mpic>;
352 dma-channel@180 {
353 compatible = "fsl,mpc8572-dma-channel",
354 "fsl,eloplus-dma-channel";
355 reg = <0x180 0x80>;
356 cell-index = <3>;
357 interrupt-parent = <&mpic>;
363 #address-cells = <1>;
364 #size-cells = <1>;
365 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
366 reg = <0x21300 0x4>;
368 cell-index = <0>;
369 dma-channel@0 {
370 compatible = "fsl,mpc8572-dma-channel",
371 "fsl,eloplus-dma-channel";
372 reg = <0x0 0x80>;
373 cell-index = <0>;
374 interrupt-parent = <&mpic>;
377 dma-channel@80 {
378 compatible = "fsl,mpc8572-dma-channel",
379 "fsl,eloplus-dma-channel";
380 reg = <0x80 0x80>;
381 cell-index = <1>;
382 interrupt-parent = <&mpic>;
385 dma-channel@100 {
386 compatible = "fsl,mpc8572-dma-channel",
387 "fsl,eloplus-dma-channel";
388 reg = <0x100 0x80>;
389 cell-index = <2>;
390 interrupt-parent = <&mpic>;
393 dma-channel@180 {
394 compatible = "fsl,mpc8572-dma-channel",
395 "fsl,eloplus-dma-channel";
396 reg = <0x180 0x80>;
397 cell-index = <3>;
398 interrupt-parent = <&mpic>;
405 #address-cells = <1>;
406 #size-cells = <1>;
407 cell-index = <0>;
411 reg = <0x24000 0x1000>;
413 local-mac-address = [ 00 00 00 00 00 00 ];
415 interrupt-parent = <&mpic>;
416 tbi-handle = <&tbi0>;
417 phy-handle = <&phy0>;
418 phy-connection-type = "sgmii";
421 #address-cells = <1>;
422 #size-cells = <0>;
423 compatible = "fsl,gianfar-mdio";
424 reg = <0x520 0x20>;
426 phy0: ethernet-phy@1 {
427 interrupt-parent = <&mpic>;
429 reg = <0x1>;
431 phy1: ethernet-phy@2 {
432 interrupt-parent = <&mpic>;
434 reg = <0x2>;
436 tbi0: tbi-phy@11 {
437 reg = <0x11>;
438 device_type = "tbi-phy";
445 #address-cells = <1>;
446 #size-cells = <1>;
447 cell-index = <1>;
451 reg = <0x25000 0x1000>;
453 local-mac-address = [ 00 00 00 00 00 00 ];
455 interrupt-parent = <&mpic>;
456 tbi-handle = <&tbi1>;
457 phy-handle = <&phy1>;
458 phy-connection-type = "sgmii";
461 #address-cells = <1>;
462 #size-cells = <0>;
463 compatible = "fsl,gianfar-tbi";
464 reg = <0x520 0x20>;
466 tbi1: tbi-phy@11 {
467 reg = <0x11>;
468 device_type = "tbi-phy";
475 cell-index = <0>;
478 reg = <0x4500 0x100>;
479 clock-frequency = <0>;
481 interrupt-parent = <&mpic>;
486 cell-index = <1>;
489 reg = <0x4600 0x100>;
490 clock-frequency = <0>;
492 interrupt-parent = <&mpic>;
495 global-utilities@e0000 { //global utilities block
496 compatible = "fsl,mpc8572-guts";
497 reg = <0xe0000 0x1000>;
498 fsl,has-rstcr;
502 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
503 reg = <0x41600 0x80>;
504 msi-available-ranges = <0 0x100>;
514 interrupt-parent = <&mpic>;
520 reg = <0x30000 0x10000>;
522 interrupt-parent = <&mpic>;
523 fsl,num-channels = <4>;
524 fsl,channel-fifo-len = <24>;
525 fsl,exec-units-mask = <0x9fe>;
526 fsl,descriptor-types-mask = <0x3ab0ebf>;
530 interrupt-controller;
531 #address-cells = <0>;
532 #interrupt-cells = <2>;
533 reg = <0x40000 0x40000>;
534 compatible = "chrp,open-pic";
535 device_type = "open-pic";
539 compatible = "fsl,mpc8572-gpio";
540 reg = <0xf000 0x1000>;
542 interrupt-parent = <&mpic>;
543 #gpio-cells = <2>;
544 gpio-controller;
547 gpio-leds {
548 compatible = "gpio-leds";
553 linux,default-trigger = "heartbeat";
572 /* PME (pattern-matcher) */
574 compatible = "fsl,mpc8572-pme", "pme8572";
575 reg = <0x10000 0x5000>;
577 interrupt-parent = <&mpic>;
581 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
582 reg = <0x2f000 0x1000>;
584 interrupt-parent = <&mpic>;
588 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
589 reg = <0x15000 0x1000>;
591 interrupt-parent = <&mpic>;
595 /* PCI Express controller 3 - CompactPCI bus via PEX8112 bridge */
597 compatible = "fsl,mpc8548-pcie";
599 #interrupt-cells = <1>;
600 #size-cells = <2>;
601 #address-cells = <3>;
602 reg = <0 0xef008000 0 0x1000>;
603 bus-range = <0 255>;
606 clock-frequency = <33333333>;
607 interrupt-parent = <&mpic>;
609 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
610 interrupt-map = <
617 reg = <0x0 0x0 0x0 0x0 0x0>;
618 #size-cells = <2>;
619 #address-cells = <3>;
633 compatible = "fsl,mpc8548-pcie";
635 #interrupt-cells = <1>;
636 #size-cells = <2>;
637 #address-cells = <3>;
638 reg = <0 0xef009000 0 0x1000>;
639 bus-range = <0 255>;
642 clock-frequency = <33333333>;
643 interrupt-parent = <&mpic>;
645 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
646 interrupt-map = <
654 reg = <0x0 0x0 0x0 0x0 0x0>;
655 #size-cells = <2>;
656 #address-cells = <3>;
670 compatible = "fsl,mpc8548-pcie";
672 #interrupt-cells = <1>;
673 #size-cells = <2>;
674 #address-cells = <3>;
675 reg = <0 0xef00a000 0 0x1000>;
676 bus-range = <0 255>;
679 clock-frequency = <33333333>;
680 interrupt-parent = <&mpic>;
682 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
683 interrupt-map = <
691 reg = <0x0 0x0 0x0 0x0 0x0>;
692 #size-cells = <2>;
693 #address-cells = <3>;