1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0-only 2*724ba675SRob Herring/* 3*724ba675SRob Herring * HiSilicon Ltd. HiP01 SoC 4*724ba675SRob Herring * 5*724ba675SRob Herring * Copyright (C) 2014 HiSilicon Ltd. 6*724ba675SRob Herring * Copyright (C) 2014 Huawei Ltd. 7*724ba675SRob Herring * 8*724ba675SRob Herring * Author: Wang Long <long.wanglong@huawei.com> 9*724ba675SRob Herring */ 10*724ba675SRob Herring 11*724ba675SRob Herring/dts-v1/; 12*724ba675SRob Herring 13*724ba675SRob Herring/* First 8KB reserved for secondary core boot */ 14*724ba675SRob Herring/memreserve/ 0x80000000 0x00002000; 15*724ba675SRob Herring 16*724ba675SRob Herring#include "hip01.dtsi" 17*724ba675SRob Herring 18*724ba675SRob Herring/ { 19*724ba675SRob Herring model = "Hisilicon HIP01 Development Board"; 20*724ba675SRob Herring compatible = "hisilicon,hip01-ca9x2", "hisilicon,hip01"; 21*724ba675SRob Herring 22*724ba675SRob Herring cpus { 23*724ba675SRob Herring #address-cells = <1>; 24*724ba675SRob Herring #size-cells = <0>; 25*724ba675SRob Herring enable-method = "hisilicon,hip01-smp"; 26*724ba675SRob Herring 27*724ba675SRob Herring cpu@0 { 28*724ba675SRob Herring device_type = "cpu"; 29*724ba675SRob Herring compatible = "arm,cortex-a9"; 30*724ba675SRob Herring reg = <0>; 31*724ba675SRob Herring }; 32*724ba675SRob Herring 33*724ba675SRob Herring cpu@1 { 34*724ba675SRob Herring device_type = "cpu"; 35*724ba675SRob Herring compatible = "arm,cortex-a9"; 36*724ba675SRob Herring reg = <1>; 37*724ba675SRob Herring }; 38*724ba675SRob Herring }; 39*724ba675SRob Herring 40*724ba675SRob Herring memory@80000000 { 41*724ba675SRob Herring device_type = "memory"; 42*724ba675SRob Herring reg = <0x80000000 0x80000000>; 43*724ba675SRob Herring }; 44*724ba675SRob Herring}; 45*724ba675SRob Herring 46*724ba675SRob Herring&uart0 { 47*724ba675SRob Herring status = "okay"; 48*724ba675SRob Herring}; 49