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/linux/Documentation/devicetree/bindings/mmc/
H A Dmarvell,xenon-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/marvell,xenon-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Xenon SDHCI Controller
11 mmc-controller.yaml and the properties used by the Xenon implementation.
20 - Ulf Hansson <ulf.hansson@linaro.org>
25 - enum:
26 - marvell,armada-cp110-sdhci
27 - marvell,armada-ap806-sdhci
[all …]
H A Dsdhci-am654.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
H A Dsdhci-st.txt1 * STMicroelectronics sdhci-st MMC/SD controller
5 used by the sdhci-st driver.
8 - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
13 - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
14 See: Documentation/devicetree/bindings/resource-names.txt
15 - clocks: Phandle to the clock.
16 See: Documentation/devicetree/bindings/clock/clock-bindings.txt
18 - interrupts: One mmc interrupt should be described here.
19 - interrupt-names: Should be "mmcirq".
21 - pinctrl-names: A pinctrl state names "default" must be defined.
[all …]
H A Dnvidia,tegra20-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
23 - enum:
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
[all …]
H A Dbrcm,iproc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/brcm,iproc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom IPROC SDHCI controller
10 - Ray Jui <ray.jui@broadcom.com>
11 - Scott Branden <scott.branden@broadcom.com>
12 - Nicolas Saenz Julienne <nsaenz@kernel.org>
15 - $ref: mmc-controller.yaml#
20 - brcm,bcm2835-sdhci
[all …]
H A Daspeed,sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later
4 ---
5 $id: http://devicetree.org/schemas/mmc/aspeed,sdhci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Jeffery <andrew@aj.id.au>
12 - Ryan Chen <ryanchen.aspeed@gmail.com>
16 Host Specification v2.00, with 1 or 4 bit data buses, or an 8 bit data bus if
26 - aspeed,ast2400-sd-controller
27 - aspeed,ast2500-sd-controller
28 - aspeed,ast2600-sd-controller
[all …]
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arasan SDHCI Controller
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
[all …]
H A Dmicrochip,dw-sparx5-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: mmc-controller.yaml
13 - Lars Povlsen <lars.povlsen@microchip.com>
18 const: microchip,dw-sparx5-sdhci
29 Handle to "core" clock for the sdhci controller.
31 clock-names:
33 - const: core
[all …]
H A Dnuvoton,ma35d1-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nuvoton,ma35d1-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shan-Chun Hung <shanchun1218@gmail.com>
13 - $ref: sdhci-common.yaml#
18 - nuvoton,ma35d1-sdhci
29 pinctrl-names:
32 - const: default
33 - const: state_uhs
[all …]
H A Dsprd,sdhci-r11.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Spreadtrum SDHCI controller
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
16 const: sprd,sdhci-r11
27 - description: SDIO source clock
[all …]
H A Dsnps,dwcmshc-sdhci.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/mmc/snps,dwcmshc-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
11 - Jisheng Zhang <Jisheng.Zhang@synaptics.com>
16 - items:
17 - enum:
18 - rockchip,rk3528-dwcmshc
19 - rockchip,rk3562-dwcmshc
[all …]
/linux/drivers/mmc/host/
H A Dsdhci-of-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
18 #include "sdhci-pltfm.h"
28 #define ASPEED_SDC_S1_PHASE_OUT_EN GENMASK(9, 8)
85 * -----|-------------|----------|------------
108 writel(cap_val, sdc->regs + mirror_reg_offset); in aspeed_sdc_set_slot_capability()
112 struct aspeed_sdhci *sdhci, in aspeed_sdc_configure_8bit_mode() argument
117 /* Set/clear 8 bit mode */ in aspeed_sdc_configure_8bit_mode()
118 spin_lock(&sdc->lock); in aspeed_sdc_configure_8bit_mode()
119 info = readl(sdc->regs + ASPEED_SDC_INFO); in aspeed_sdc_configure_8bit_mode()
121 info |= sdhci->width_mask; in aspeed_sdc_configure_8bit_mode()
[all …]
H A Dsdhci-pltfm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sdhci-pltfm.c Support for SDHCI platform devices
14 * SDHCI platform devices
16 * Inspired by sdhci-pci.c, by Pierre Ossman
25 #include "sdhci-pltfm.h"
31 return clk_get_rate(pltfm_host->clk); in sdhci_pltfm_clk_get_max_clock()
44 if (device_property_present(dev, "sdhci,wp-inverted") || in sdhci_wp_inverted()
45 device_property_present(dev, "wp-inverted")) in sdhci_wp_inverted()
48 /* Old device trees don't have the wp-inverted property. */ in sdhci_wp_inverted()
58 struct device *dev = &pdev->dev; in sdhci_get_compatibility()
[all …]
H A Dsdhci-of-k1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2023-2025 SpacemiT (Hangzhou) Technology Co. Ltd
20 #include "sdhci.h"
21 #include "sdhci-pltfm.h"
26 #define SDHC_ENHANCE_STROBE_EN BIT(8)
52 #define SDHC_DLL_REG2_CTRL GENMASK(15, 8)
101 if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) in spacemit_sdhci_reset()
115 if (!(host->mmc->caps2 & MMC_CAP2_NO_SDIO)) in spacemit_sdhci_set_uhs_signaling()
121 struct mmc_host *mmc = host->mmc; in spacemit_sdhci_set_clock()
123 if (mmc->ios.timing <= MMC_TIMING_UHS_SDR50) in spacemit_sdhci_set_clock()
[all …]
H A Dsdhci-esdhc-mcf.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/platform_data/mmc-esdhc-mcf.h>
13 #include "sdhci-pltfm.h"
14 #include "sdhci-esdhc.h"
49 void __iomem *base = host->ioaddr + (reg & ~3); in esdhc_clrset_be()
62 * Note: mcf is big-endian, single bytes need to be accessed at big endian
67 void __iomem *base = host->ioaddr + (reg & ~3); in esdhc_mcf_writeb_be()
74 u8 tmp = readb(host->ioaddr + SDHCI_HOST_CONTROL + 1); in esdhc_mcf_writeb_be()
84 host_ctrl |= (dma_bits << 8); in esdhc_mcf_writeb_be()
85 writel(host_ctrl, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_mcf_writeb_be()
[all …]
H A Dsdhci-of-ma35d1.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Shan-Chun Hung <shanchun1218@gmail.com>
16 #include <linux/dma-mapping.h>
32 #include "sdhci-pltfm.h"
33 #include "sdhci.h"
77 if (likely(!len || (ALIGN(addr, SZ_128M) == ALIGN(addr + len - 1, SZ_128M)))) { in ma35_adma_write_desc()
82 offset = addr & (SZ_128M - 1); in ma35_adma_write_desc()
83 tmplen = SZ_128M - offset; in ma35_adma_write_desc()
87 len -= tmplen; in ma35_adma_write_desc()
115 switch (ios->signal_voltage) { in ma35_start_signal_voltage_switch()
[all …]
H A Dsdhci-pxav2.c1 // SPDX-License-Identifier: GPL-2.0-only
26 #include "sdhci.h"
27 #include "sdhci-pltfm.h"
37 #define SDCLK_SEL_SHIFT 8
55 struct platform_device *pdev = to_platform_device(mmc_dev(host->mmc)); in pxav2_reset()
56 struct sdhci_pxa_platdata *pdata = pdev->dev.platform_data; in pxav2_reset()
67 if (pdata && pdata->clk_delay_sel == 1) { in pxav2_reset()
68 tmp = readw(host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
71 tmp |= (pdata->clk_delay_cycles & SDCLK_DELAY_MASK) in pxav2_reset()
76 writew(tmp, host->ioaddr + SD_CLOCK_BURST_SIZE_SETUP); in pxav2_reset()
[all …]
/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-ast2600-evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
11 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
26 reserved-memory {
27 #address-cells = <1>;
28 #size-cells = <1>;
34 compatible = "shared-dma-pool";
41 compatible = "shared-dma-pool";
[all …]
/linux/arch/powerpc/boot/dts/
H A Dwii.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2008-2009 The GameCube Linux Team
10 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
15 * This is commented-out for now.
25 #address-cells = <1>;
26 #size-cells = <1>;
29 bootargs = "root=/dev/mmcblk0p2 rootwait udbg-immortal";
34 reg = <0x00000000 0x01800000 /* MEM1 24MB 1T-SRAM */
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dpinctrl_spear.txt4 - compatible : "st,spear300-pinmux"
5 : "st,spear310-pinmux"
6 : "st,spear320-pinmux"
7 : "st,spear1310-pinmux"
8 : "st,spear1340-pinmux"
9 - reg : Address range of the pinctrl registers
10 - st,pinmux-mode: Mandatory for SPEAr300 and SPEAr320 and invalid for others.
11 - Its values for SPEAr300:
12 - NAND_MODE : <0>
13 - NOR_MODE : <1>
[all …]
/linux/arch/arm/boot/dts/renesas/
H A Dr9a06g032.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
23 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
33 enable-method = "renesas,r9a06g032-smp";
[all …]
/linux/arch/arm64/boot/dts/qcom/
H A Dsm6115p-lenovo-j606f.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 /dts-v1/;
14 chassis-type = "tablet";
17 qcom,msm-id = <445 0x10000>, <420 0x10000>;
18 qcom,board-id = <34 3>;
25 #address-cells = <2>;
26 #size-cells = <2>;
30 compatible = "simple-framebuffer";
40 gpio-keys {
41 compatible = "gpio-keys";
[all …]
/linux/include/linux/platform_data/
H A Dpxa_sdhci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * PXA Platform - SDHCI platform data definitions
17 /* card always wired to host, like on-chip emmc */
19 /* Board design supports 8-bit data on SD/SDIO BUS */
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3566-anbernic-rg-arc-d.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/pinctrl/rockchip.h>
8 #include "rk3566-anbernic-rg-arc.dtsi"
11 model = "Anbernic RG ARC-D";
12 compatible = "anbernic,rg-arc-d", "rockchip,rk3566";
15 mmc0 = &sdhci;
23 pinctrl-0 = <&i2c2m1_xfer>;
[all …]
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mt7621.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "pinctrl-mtmips.h"
18 #define MT7621_GPIO_MODE_WDT_SHIFT 8
65 FUNC("sdhci", 0, 41, 8),
66 FUNC("nand2", 2, 41, 8),
87 GRP_G("sdhci", sdhci_grp, MT7621_GPIO_MODE_SDHCI_MASK,
99 { .compatible = "ralink,mt7621-pinctrl" },
100 { .compatible = "ralink,rt2880-pinmux" },
108 .name = "mt7621-pinctrl",

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