xref: /linux/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip Sparx5 Mobile Storage Host Controller
8
9allOf:
10  - $ref: mmc-controller.yaml
11
12maintainers:
13  - Lars Povlsen <lars.povlsen@microchip.com>
14
15# Everything else is described in the common file
16properties:
17  compatible:
18    const: microchip,dw-sparx5-sdhci
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  clocks:
27    maxItems: 1
28    description:
29      Handle to "core" clock for the sdhci controller.
30
31  clock-names:
32    items:
33      - const: core
34
35  microchip,clock-delay:
36    description: Delay clock to card to meet setup time requirements.
37      Each step increase by 1.25ns.
38    $ref: /schemas/types.yaml#/definitions/uint32
39    minimum: 1
40    maximum: 15
41
42required:
43  - compatible
44  - reg
45  - interrupts
46  - clocks
47  - clock-names
48
49unevaluatedProperties: false
50
51examples:
52  - |
53    #include <dt-bindings/interrupt-controller/arm-gic.h>
54    #include <dt-bindings/clock/microchip,sparx5.h>
55    sdhci0: mmc@600800000 {
56        compatible = "microchip,dw-sparx5-sdhci";
57        reg = <0x00800000 0x1000>;
58        pinctrl-0 = <&emmc_pins>;
59        pinctrl-names = "default";
60        clocks = <&clks CLK_ID_AUX1>;
61        clock-names = "core";
62        assigned-clocks = <&clks CLK_ID_AUX1>;
63        assigned-clock-rates = <800000000>;
64        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
65        bus-width = <8>;
66        microchip,clock-delay = <10>;
67    };
68