1*cb1f1c7dSStanislav Jakubek# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2*cb1f1c7dSStanislav Jakubek%YAML 1.2 3*cb1f1c7dSStanislav Jakubek--- 4*cb1f1c7dSStanislav Jakubek$id: http://devicetree.org/schemas/mmc/sprd,sdhci-r11.yaml# 5*cb1f1c7dSStanislav Jakubek$schema: http://devicetree.org/meta-schemas/core.yaml# 6*cb1f1c7dSStanislav Jakubek 7*cb1f1c7dSStanislav Jakubektitle: Spreadtrum SDHCI controller 8*cb1f1c7dSStanislav Jakubek 9*cb1f1c7dSStanislav Jakubekmaintainers: 10*cb1f1c7dSStanislav Jakubek - Orson Zhai <orsonzhai@gmail.com> 11*cb1f1c7dSStanislav Jakubek - Baolin Wang <baolin.wang7@gmail.com> 12*cb1f1c7dSStanislav Jakubek - Chunyan Zhang <zhang.lyra@gmail.com> 13*cb1f1c7dSStanislav Jakubek 14*cb1f1c7dSStanislav Jakubekproperties: 15*cb1f1c7dSStanislav Jakubek compatible: 16*cb1f1c7dSStanislav Jakubek const: sprd,sdhci-r11 17*cb1f1c7dSStanislav Jakubek 18*cb1f1c7dSStanislav Jakubek reg: 19*cb1f1c7dSStanislav Jakubek maxItems: 1 20*cb1f1c7dSStanislav Jakubek 21*cb1f1c7dSStanislav Jakubek interrupts: 22*cb1f1c7dSStanislav Jakubek maxItems: 1 23*cb1f1c7dSStanislav Jakubek 24*cb1f1c7dSStanislav Jakubek clocks: 25*cb1f1c7dSStanislav Jakubek minItems: 2 26*cb1f1c7dSStanislav Jakubek items: 27*cb1f1c7dSStanislav Jakubek - description: SDIO source clock 28*cb1f1c7dSStanislav Jakubek - description: gate clock for enabling/disabling the device 29*cb1f1c7dSStanislav Jakubek - description: gate clock controlling the device for some special platforms (optional) 30*cb1f1c7dSStanislav Jakubek 31*cb1f1c7dSStanislav Jakubek clock-names: 32*cb1f1c7dSStanislav Jakubek minItems: 2 33*cb1f1c7dSStanislav Jakubek items: 34*cb1f1c7dSStanislav Jakubek - const: sdio 35*cb1f1c7dSStanislav Jakubek - const: enable 36*cb1f1c7dSStanislav Jakubek - const: 2x_enable 37*cb1f1c7dSStanislav Jakubek 38*cb1f1c7dSStanislav Jakubek pinctrl-0: 39*cb1f1c7dSStanislav Jakubek description: default/high speed pin control 40*cb1f1c7dSStanislav Jakubek maxItems: 1 41*cb1f1c7dSStanislav Jakubek 42*cb1f1c7dSStanislav Jakubek pinctrl-1: 43*cb1f1c7dSStanislav Jakubek description: UHS mode pin control 44*cb1f1c7dSStanislav Jakubek maxItems: 1 45*cb1f1c7dSStanislav Jakubek 46*cb1f1c7dSStanislav Jakubek pinctrl-names: 47*cb1f1c7dSStanislav Jakubek minItems: 1 48*cb1f1c7dSStanislav Jakubek items: 49*cb1f1c7dSStanislav Jakubek - const: default 50*cb1f1c7dSStanislav Jakubek - const: state_uhs 51*cb1f1c7dSStanislav Jakubek 52*cb1f1c7dSStanislav JakubekpatternProperties: 53*cb1f1c7dSStanislav Jakubek "^sprd,phy-delay-(legacy|mmc-(ddr52|highspeed|hs[24]00|hs400es)|sd-(highspeed|uhs-sdr(50|104)))$": 54*cb1f1c7dSStanislav Jakubek $ref: /schemas/types.yaml#/definitions/uint32-array 55*cb1f1c7dSStanislav Jakubek items: 56*cb1f1c7dSStanislav Jakubek - description: clock data write line delay value 57*cb1f1c7dSStanislav Jakubek - description: clock read command line delay value 58*cb1f1c7dSStanislav Jakubek - description: clock read data positive edge delay value 59*cb1f1c7dSStanislav Jakubek - description: clock read data negative edge delay value 60*cb1f1c7dSStanislav Jakubek description: 61*cb1f1c7dSStanislav Jakubek PHY DLL delays are used to delay the data valid window, and align 62*cb1f1c7dSStanislav Jakubek the window to the sampling clock. Each cell's delay value unit is 63*cb1f1c7dSStanislav Jakubek cycle of the PHY clock. 64*cb1f1c7dSStanislav Jakubek 65*cb1f1c7dSStanislav Jakubekrequired: 66*cb1f1c7dSStanislav Jakubek - compatible 67*cb1f1c7dSStanislav Jakubek - reg 68*cb1f1c7dSStanislav Jakubek - interrupts 69*cb1f1c7dSStanislav Jakubek - clocks 70*cb1f1c7dSStanislav Jakubek - clock-names 71*cb1f1c7dSStanislav Jakubek 72*cb1f1c7dSStanislav JakubekallOf: 73*cb1f1c7dSStanislav Jakubek - $ref: sdhci-common.yaml# 74*cb1f1c7dSStanislav Jakubek 75*cb1f1c7dSStanislav JakubekunevaluatedProperties: false 76*cb1f1c7dSStanislav Jakubek 77*cb1f1c7dSStanislav Jakubekexamples: 78*cb1f1c7dSStanislav Jakubek - | 79*cb1f1c7dSStanislav Jakubek #include <dt-bindings/clock/sprd,sc9860-clk.h> 80*cb1f1c7dSStanislav Jakubek #include <dt-bindings/interrupt-controller/arm-gic.h> 81*cb1f1c7dSStanislav Jakubek #include <dt-bindings/interrupt-controller/irq.h> 82*cb1f1c7dSStanislav Jakubek 83*cb1f1c7dSStanislav Jakubek mmc@50430000 { 84*cb1f1c7dSStanislav Jakubek compatible = "sprd,sdhci-r11"; 85*cb1f1c7dSStanislav Jakubek reg = <0x50430000 0x1000>; 86*cb1f1c7dSStanislav Jakubek interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 87*cb1f1c7dSStanislav Jakubek 88*cb1f1c7dSStanislav Jakubek clocks = <&aon_prediv CLK_EMMC_2X>, 89*cb1f1c7dSStanislav Jakubek <&apahb_gate CLK_EMMC_EB>, 90*cb1f1c7dSStanislav Jakubek <&aon_gate CLK_EMMC_2X_EN>; 91*cb1f1c7dSStanislav Jakubek clock-names = "sdio", "enable", "2x_enable"; 92*cb1f1c7dSStanislav Jakubek 93*cb1f1c7dSStanislav Jakubek pinctrl-0 = <&sd0_pins_default>; 94*cb1f1c7dSStanislav Jakubek pinctrl-1 = <&sd0_pins_uhs>; 95*cb1f1c7dSStanislav Jakubek pinctrl-names = "default", "state_uhs"; 96*cb1f1c7dSStanislav Jakubek 97*cb1f1c7dSStanislav Jakubek bus-width = <8>; 98*cb1f1c7dSStanislav Jakubek cap-mmc-hw-reset; 99*cb1f1c7dSStanislav Jakubek mmc-hs400-enhanced-strobe; 100*cb1f1c7dSStanislav Jakubek mmc-hs400-1_8v; 101*cb1f1c7dSStanislav Jakubek mmc-hs200-1_8v; 102*cb1f1c7dSStanislav Jakubek mmc-ddr-1_8v; 103*cb1f1c7dSStanislav Jakubek non-removable; 104*cb1f1c7dSStanislav Jakubek no-sdio; 105*cb1f1c7dSStanislav Jakubek no-sd; 106*cb1f1c7dSStanislav Jakubek 107*cb1f1c7dSStanislav Jakubek sprd,phy-delay-mmc-ddr52 = <0x3f 0x75 0x14 0x14>; 108*cb1f1c7dSStanislav Jakubek sprd,phy-delay-mmc-hs200 = <0x0 0x8c 0x8c 0x8c>; 109*cb1f1c7dSStanislav Jakubek sprd,phy-delay-mmc-hs400 = <0x44 0x7f 0x2e 0x2e>; 110*cb1f1c7dSStanislav Jakubek sprd,phy-delay-mmc-hs400es = <0x3f 0x3f 0x2e 0x2e>; 111*cb1f1c7dSStanislav Jakubek }; 112*cb1f1c7dSStanislav Jakubek... 113