| /linux/drivers/clk/socfpga/ |
| H A D | clk-pll-s10.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
44 unsigned long fdiv, reg, rdiv, qdiv; in n5x_clk_pll_recalc_rate() local
47 /* read VCO1 reg for numerator and denominator */ in n5x_clk_pll_recalc_rate()
48 reg = readl(socfpgaclk->hw.reg + 0x8); in n5x_clk_pll_recalc_rate()
49 fdiv = (reg & SOCFPGA_N5X_PLLDIV_FDIV_MASK) >> SOCFPGA_N5X_PLLDIV_FDIV_SHIFT; in n5x_clk_pll_recalc_rate()
50 rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK); in n5x_clk_pll_recalc_rate()
51 qdiv = (reg & SOCFPGA_N5X_PLLDIV_QDIV_MASK) >> SOCFPGA_N5X_PLLDIV_QDIV_SHIFT; in n5x_clk_pll_recalc_rate()
55 qdiv--; in n5x_clk_pll_recalc_rate()
[all …]
|
| H A D | clk-periph-s10.c | 1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
9 #include "stratix10-clk.h"
23 unsigned long shift = socfpgaclk->shift; in n5x_clk_peri_c_clk_recalc_rate()
26 val = readl(socfpgaclk->hw.reg); in n5x_clk_peri_c_clk_recalc_rate()
40 val = readl(socfpgaclk->hw.reg); in clk_peri_c_clk_recalc_rate()
41 val &= GENMASK(SWCTRLBTCLKSEN_SHIFT - 1, 0); in clk_peri_c_clk_recalc_rate()
53 if (socfpgaclk->fixed_div) { in clk_peri_cnt_clk_recalc_rate()
54 div = socfpgaclk->fixed_div; in clk_peri_cnt_clk_recalc_rate()
56 if (socfpgaclk->hw.reg) in clk_peri_cnt_clk_recalc_rate()
[all …]
|
| H A D | clk-pll.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2011-2012 Calxeda, Inc.
4 * Copyright (C) 2012-2013 Altera Corporation <www.altera.com>
6 * Based from clk-highbank.c
9 #include <linux/clk-provider.h>
42 u32 divf, divq, reg; in clk_pll_recalc_rate() local
46 reg = readl(socfpgaclk->hw.reg); in clk_pll_recalc_rate()
51 divf = (reg & SOCFPGA_PLL_DIVF_MASK) >> SOCFPGA_PLL_DIVF_SHIFT; in clk_pll_recalc_rate()
52 divq = (reg & SOCFPGA_PLL_DIVQ_MASK) >> SOCFPGA_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
63 pll_src = readl(socfpgaclk->hw.reg); in clk_pll_get_parent()
[all …]
|
| /linux/drivers/gpu/drm/nouveau/nvkm/subdev/bios/ |
| H A D | init.c | 31 #include <subdev/bios/init.h>
42 nvkm_printk(init->subdev, lvl, info, "0x%08x[%c]: "fmt, \
43 init->offset, init_exec(init) ? \
44 '0' + (init->nested - 1) : ' ', ##args); \
47 if (init->subdev->debug >= NV_DBG_TRACE) \
55 * init parser control flow helpers
59 init_exec(struct nvbios_init *init) in init_exec() argument
61 return (init->execute == 1) || ((init->execute & 5) == 5); in init_exec()
65 init_exec_set(struct nvbios_init *init, bool exec) in init_exec_set() argument
67 if (exec) init->execute &= 0xfd; in init_exec_set()
[all …]
|
| /linux/drivers/clk/x86/ |
| H A D | clk-cgu.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
8 #include <linux/clk-provider.h>
12 #include "clk-cgu.h"
14 #define GATE_HW_REG_STAT(reg) ((reg) + 0x0) argument
15 #define GATE_HW_REG_EN(reg) ((reg) + 0x4) argument
16 #define GATE_HW_REG_DIS(reg) ((reg) + 0x8) argument
29 if (list->div_flags & CLOCK_FLAG_VAL_INIT) in lgm_clk_register_fixed()
30 lgm_set_clk_val(ctx->membase, list->div_off, list->div_shift, in lgm_clk_register_fixed()
31 list->div_width, list->div_val); in lgm_clk_register_fixed()
[all …]
|
| /linux/drivers/clk/ |
| H A D | clk-axm5516.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
39 u32 reg; member
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
[all …]
|
| H A D | clk-k210.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #define pr_fmt(fmt) "k210-clk: " fmt
15 #include <linux/clk-provider.h>
18 #include <soc/canaan/k210-sysctl.h>
20 #include <dt-bindings/clock/k210-clk.h>
291 void __iomem *reg; member
306 u32 reg; member
322 * struct k210_sysclk - sysclk driver data
344 u32 reg = readl(regs + K210_SYSCTL_SEL0); in k210_aclk_set_selector() local
[all …]
|
| H A D | clk-highbank.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011-2012 Calxeda, Inc.
9 #include <linux/clk-provider.h>
39 void __iomem *reg; member
46 u32 reg; in clk_pll_prepare() local
48 reg = readl(hbclk->reg); in clk_pll_prepare()
49 reg &= ~HB_PLL_RESET; in clk_pll_prepare()
50 writel(reg, hbclk->reg); in clk_pll_prepare()
52 while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0) in clk_pll_prepare()
54 while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0) in clk_pll_prepare()
[all …]
|
| H A D | clk-mux.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
21 * prepare - clk_prepare only ensures that parents are prepared
22 * enable - clk_enable only ensures that parents are enabled
23 * rate - rate is only affected by parent switching. No clk_set_rate support
24 * parent - parent is adjustable through clk_set_parent
29 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl()
30 return ioread32be(mux->reg); in clk_mux_readl()
32 return readl(mux->reg); in clk_mux_readl()
[all …]
|
| /linux/drivers/clk/axs10x/ |
| H A D | pll_clock.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
28 * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
33 * reg should be an u32 variable.
36 #define PLL_REG_GET_LOW(reg) \ argument
37 (((reg) & (0x3F << 0)) >> 0)
38 #define PLL_REG_GET_HIGH(reg) \ argument
39 (((reg) & (0x3F << 6)) >> 6)
40 #define PLL_REG_GET_EDGE(reg) \ argument
41 (((reg) & (BIT(12))) ? 1 : 0)
[all …]
|
| /linux/drivers/clk/rockchip/ |
| H A D | clk-inverter.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
7 #include <linux/clk-provider.h>
15 void __iomem *reg; member
30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase()
45 return -EINVAL; in rockchip_inv_set_phase()
48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase()
49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase()
50 inv_clock->reg); in rockchip_inv_set_phase()
53 u32 reg; in rockchip_inv_set_phase() local
55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase()
[all …]
|
| /linux/drivers/clk/imx/ |
| H A D | clk-lpcg-scu.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
16 #include "clk-scu.h"
25 * struct clk_lpcg_scu - Description of LPCG clock
28 * @reg: register of this LPCG clock
36 void __iomem *reg; member
46 /* e10858 -LPCG clock gating register synchronization errata */
47 static void lpcg_e10858_writel(unsigned long rate, void __iomem *reg, u32 val) in lpcg_e10858_writel() argument
49 writel(val, reg); in lpcg_e10858_writel()
57 * back-to-back writes. in lpcg_e10858_writel()
[all …]
|
| H A D | clk-gate2.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
9 #include <linux/clk-provider.h>
22 * prepare - clk_(un)prepare only ensures parent is (un)prepared
23 * enable - clk_enable and clk_disable are functional & control gating
24 * rate - inherits rate from parent. No clk_set_rate support
25 * parent - fixed parent. No clk_set_parent support
30 void __iomem *reg; member
44 u32 reg; in clk_gate2_do_shared_clks() local
[all …]
|
| H A D | clk-gate-93.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
20 * 0b000 - LPCG will be OFF in any CPU mode.
21 * 0b100 - LPCG will be ON in any CPU mode.
37 void __iomem *reg; member
52 val = readl(gate->reg + AUTHEN_OFFSET); in imx93_clk_gate_do_hardware()
55 writel(val, gate->reg + LPM_CUR_OFFSET); in imx93_clk_gate_do_hardware()
57 val = readl(gate->reg + DIRECT_OFFSET); in imx93_clk_gate_do_hardware()
58 val &= ~(gate->mask << gate->bit_idx); in imx93_clk_gate_do_hardware()
60 val |= (gate->val & gate->mask) << gate->bit_idx; in imx93_clk_gate_do_hardware()
[all …]
|
| H A D | clk-pfdv2.c | 1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
19 * struct clk_pfdv2 - IMX PFD clock
21 * @reg: PFD register address
29 void __iomem *reg; member
47 return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit), in clk_pfdv2_wait()
58 val = readl_relaxed(pfd->reg); in clk_pfdv2_enable()
59 val &= ~(1 << pfd->gate_bit); in clk_pfdv2_enable()
60 writel_relaxed(val, pfd->reg); in clk_pfdv2_enable()
73 val = readl_relaxed(pfd->reg); in clk_pfdv2_disable()
[all …]
|
| /linux/drivers/clk/tegra/ |
| H A D | clk-super.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
28 #define super_state_to_src_shift(m, s) ((m->width * s))
29 #define super_state_to_src_mask(m) (((1 << m->width) - 1))
40 val = readl_relaxed(mux->reg); in clk_super_get_parent()
56 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
57 (source == mux->pllx_index)) in clk_super_get_parent()
58 source = mux->div2_index; in clk_super_get_parent()
71 if (mux->lock) in clk_super_set_parent()
72 spin_lock_irqsave(mux->lock, flags); in clk_super_set_parent()
[all …]
|
| H A D | clk-pll-out.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
15 #define pll_out_enb(p) (BIT(p->enb_bit_idx))
16 #define pll_out_rst(p) (BIT(p->rst_bit_idx))
21 u32 val = readl_relaxed(pll_out->reg); in clk_pll_out_is_enabled()
36 if (pll_out->lock) in clk_pll_out_enable()
37 spin_lock_irqsave(pll_out->lock, flags); in clk_pll_out_enable()
39 val = readl_relaxed(pll_out->reg); in clk_pll_out_enable()
43 writel_relaxed(val, pll_out->reg); in clk_pll_out_enable()
46 if (pll_out->lock) in clk_pll_out_enable()
[all …]
|
| H A D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
14 #define pll_out_override(p) (BIT((p->shift - 6)))
15 #define div_mask(d) ((1 << (d->width)) - 1)
16 #define get_mul(d) (1 << d->frac_width)
26 div = div_frac_get(rate, parent_rate, divider->width, in get_div()
27 divider->frac_width, divider->flags); in get_div()
39 u32 reg; in clk_frac_div_recalc_rate() local
43 reg = readl_relaxed(divider->reg); in clk_frac_div_recalc_rate()
45 if ((divider->flags & TEGRA_DIVIDER_UART) && in clk_frac_div_recalc_rate()
[all …]
|
| /linux/arch/mips/boot/dts/cavium-octeon/ |
| H A D | octeon_3xxx.dts | 1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
19 <2 0x15 0xffcf 0>, /* Reg 2,21 Clear bits 4, 5 */
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
24 reg = <0>;
27 phy1: ethernet-phy@1 {
[all …]
|
| H A D | octeon_68xx.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
7 * use. Because of this, it contains a super-set of the available
11 compatible = "cavium,octeon-6880";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&ciu2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
[all …]
|
| /linux/drivers/clk/sunxi/ |
| H A D | clk-sun4i-tcon-ch1.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Maxime Ripard <maxime.ripard@free-electrons.com>
8 #include <linux/clk-provider.h>
29 void __iomem *reg; member
38 u32 reg; in tcon_ch1_disable() local
40 spin_lock_irqsave(&tclk->lock, flags); in tcon_ch1_disable()
41 reg = readl(tclk->reg); in tcon_ch1_disable()
42 reg &= ~(TCON_CH1_SCLK2_GATE_BIT | TCON_CH1_SCLK1_GATE_BIT); in tcon_ch1_disable()
43 writel(reg, tclk->reg); in tcon_ch1_disable()
44 spin_unlock_irqrestore(&tclk->lock, flags); in tcon_ch1_disable()
[all …]
|
| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun4i_hdmi_tmds_clk.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
9 #include <linux/clk-provider.h>
49 (rate - tmp_rate) < (rate - best_rate)) { in sun4i_tmds_calc_divider()
72 unsigned long rate = req->rate; in sun4i_tmds_determine_rate()
88 for (j = tmds->div_offset ?: 1; in sun4i_tmds_determine_rate()
89 j < (16 + tmds->div_offset); j++) { in sun4i_tmds_determine_rate()
103 abs(rate - rounded / i / j) < in sun4i_tmds_determine_rate()
104 abs(rate - best_parent / best_half / in sun4i_tmds_determine_rate()
115 return -EINVAL; in sun4i_tmds_determine_rate()
[all …]
|
| /linux/drivers/clk/mxs/ |
| H A D | clk-div.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <linux/clk-provider.h>
12 * struct clk_div - mxs integer divider clock
15 * @reg: register address
24 void __iomem *reg; member
40 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
48 return div->ops->determine_rate(&div->divider.hw, req); in clk_div_determine_rate()
57 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
59 ret = mxs_clk_wait(div->reg, div->busy); in clk_div_set_rate()
71 void __iomem *reg, u8 shift, u8 width, u8 busy) in mxs_clk_div() argument
[all …]
|
| /linux/drivers/clk/nxp/ |
| H A D | clk-lpc18xx-creg.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/clk-provider.h>
33 struct regmap *reg; member
50 ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, in clk_creg_32k_prepare()
67 regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, in clk_creg_32k_unprepare()
75 u32 reg; in clk_creg_32k_is_prepared() local
77 regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®); in clk_creg_32k_is_prepared()
79 return !(reg & LPC18XX_CREG_CREG0_PD32KHZ) && in clk_creg_32k_is_prepared()
80 !(reg & LPC18XX_CREG_CREG0_RESET32KHZ); in clk_creg_32k_is_prepared()
93 return regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0, in clk_creg_enable()
[all …]
|
| /linux/drivers/clk/mvebu/ |
| H A D | clk-cpu.c | 1 // SPDX-License-Identifier: GPL-2.0
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
13 #include <linux/clk-provider.h>
18 #include <linux/mvebu-pmsu.h>
52 u32 reg, div; in clk_cpu_recalc_rate() local
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate()
65 div = req->best_parent_rate / req->rate; in clk_cpu_determine_rate()
71 req->rate = req->best_parent_rate / div; in clk_cpu_determine_rate()
81 u32 reg, div; in clk_cpu_off_set_rate() local
[all …]
|