1 // SPDX-License-Identifier: GPL-2.0
7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
13 #include <linux/clk-provider.h>
18 #include <linux/mvebu-pmsu.h>
52 	u32 reg, div;  in clk_cpu_recalc_rate()  local
54 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);  in clk_cpu_recalc_rate()
55 	div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK;  in clk_cpu_recalc_rate()
65 	div = req->best_parent_rate / req->rate;  in clk_cpu_determine_rate()
71 	req->rate = req->best_parent_rate / div;  in clk_cpu_determine_rate()
81 	u32 reg, div;  in clk_cpu_off_set_rate()  local
85 	reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET)  in clk_cpu_off_set_rate()
86 		& (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8))))  in clk_cpu_off_set_rate()
87 		| (div << (cpuclk->cpu * 8));  in clk_cpu_off_set_rate()
88 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET);  in clk_cpu_off_set_rate()
90 	reload_mask = 1 << (20 + cpuclk->cpu);  in clk_cpu_off_set_rate()
92 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)  in clk_cpu_off_set_rate()
94 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_off_set_rate()
97 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET)  in clk_cpu_off_set_rate()
99 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_off_set_rate()
103 	reg &= ~(reload_mask | 1 << 24);  in clk_cpu_off_set_rate()
104 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_off_set_rate()
113 	u32 reg;  in clk_cpu_on_set_rate()  local
121 	if (!cpuclk->pmu_dfs)  in clk_cpu_on_set_rate()
122 		return -ENODEV;  in clk_cpu_on_set_rate()
126 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL2_OFFSET);  in clk_cpu_on_set_rate()
127 	fabric_div = (reg >> SYS_CTRL_CLK_DIVIDER_CTRL2_NBCLK_RATIO_SHIFT) &  in clk_cpu_on_set_rate()
140 	reg = readl(cpuclk->pmu_dfs);  in clk_cpu_on_set_rate()
141 	reg &= ~(PMU_DFS_RATIO_MASK << PMU_DFS_RATIO_SHIFT);  in clk_cpu_on_set_rate()
142 	reg |= (target_div << PMU_DFS_RATIO_SHIFT);  in clk_cpu_on_set_rate()
143 	writel(reg, cpuclk->pmu_dfs);  in clk_cpu_on_set_rate()
145 	reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_on_set_rate()
146 	reg |= (SYS_CTRL_CLK_DIVIDER_CTRL_RESET_ALL <<  in clk_cpu_on_set_rate()
148 	writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET);  in clk_cpu_on_set_rate()
150 	return mvebu_pmsu_dfs_request(cpuclk->cpu);  in clk_cpu_on_set_rate()
156 	if (__clk_is_enabled(hwclk->clk))  in clk_cpu_set_rate()
177 		pr_err("%s: clock-complex base register not set\n",  in of_cpu_clk_setup()
183 		pr_warn("%s: pmu-dfs base register not set, dynamic frequency scaling not available\n",  in of_cpu_clk_setup()
195 		struct clk_init_data init;  in of_cpu_clk_setup()  local
210 		cpuclk[cpu].hw.init = &init;  in of_cpu_clk_setup()
212 		init.name = cpuclk[cpu].clk_name;  in of_cpu_clk_setup()
213 		init.ops = &cpu_ops;  in of_cpu_clk_setup()
214 		init.flags = 0;  in of_cpu_clk_setup()
215 		init.parent_names = &cpuclk[cpu].parent_name;  in of_cpu_clk_setup()
216 		init.num_parents = 1;  in of_cpu_clk_setup()
230 	while(ncpus--)  in of_cpu_clk_setup()
238 CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
246 CLK_OF_DECLARE(mv98dx3236_cpu_clock, "marvell,mv98dx3236-cpu-clock",