1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
19  * struct clk_pfdv2 - IMX PFD clock
21  * @reg:	PFD register address
29 	void __iomem	*reg;  member
47 	return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit),  in clk_pfdv2_wait()
58 	val = readl_relaxed(pfd->reg);  in clk_pfdv2_enable()
59 	val &= ~(1 << pfd->gate_bit);  in clk_pfdv2_enable()
60 	writel_relaxed(val, pfd->reg);  in clk_pfdv2_enable()
73 	val = readl_relaxed(pfd->reg);  in clk_pfdv2_disable()
74 	val |= (1 << pfd->gate_bit);  in clk_pfdv2_disable()
75 	writel_relaxed(val, pfd->reg);  in clk_pfdv2_disable()
86 	frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)  in clk_pfdv2_recalc_rate()
107 					req->best_parent_rate  in clk_pfdv2_determine_rate()
109 	unsigned long best_rate = -1UL, rate = req->rate;  in clk_pfdv2_determine_rate()
110 	unsigned long best_parent_rate = req->best_parent_rate;  in clk_pfdv2_determine_rate()
130 		if (abs(tmp - req->rate) < abs(best_rate - req->rate)) {  in clk_pfdv2_determine_rate()
136 	req->best_parent_rate = best_parent_rate;  in clk_pfdv2_determine_rate()
137 	req->rate = best_rate;  in clk_pfdv2_determine_rate()
146 	if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit))  in clk_pfdv2_is_enabled()
162 		return -EINVAL;  in clk_pfdv2_set_rate()
169 	 * ops especially for 'assigned-clock-xxx'. In order  in clk_pfdv2_set_rate()
185 	val = readl_relaxed(pfd->reg);  in clk_pfdv2_set_rate()
186 	val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off);  in clk_pfdv2_set_rate()
187 	val |= frac << pfd->frac_off;  in clk_pfdv2_set_rate()
188 	writel_relaxed(val, pfd->reg);  in clk_pfdv2_set_rate()
204 			     const char *parent_name, void __iomem *reg, u8 idx)  in imx_clk_hw_pfdv2()  argument
206 	struct clk_init_data init;  in imx_clk_hw_pfdv2()  local
215 		return ERR_PTR(-ENOMEM);  in imx_clk_hw_pfdv2()
217 	pfd->reg = reg;  in imx_clk_hw_pfdv2()
218 	pfd->gate_bit = (idx + 1) * 8 - 1;  in imx_clk_hw_pfdv2()
219 	pfd->vld_bit = pfd->gate_bit - 1;  in imx_clk_hw_pfdv2()
220 	pfd->frac_off = idx * 8;  in imx_clk_hw_pfdv2()
222 	init.name = name;  in imx_clk_hw_pfdv2()
223 	init.ops = &clk_pfdv2_ops;  in imx_clk_hw_pfdv2()
224 	init.parent_names = &parent_name;  in imx_clk_hw_pfdv2()
225 	init.num_parents = 1;  in imx_clk_hw_pfdv2()
227 		init.flags = CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT;  in imx_clk_hw_pfdv2()
229 		init.flags = CLK_SET_RATE_GATE;  in imx_clk_hw_pfdv2()
231 	pfd->hw.init = &init;  in imx_clk_hw_pfdv2()
233 	hw = &pfd->hw;  in imx_clk_hw_pfdv2()