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/linux/Documentation/devicetree/bindings/net/
H A Drealtek,rtl9301-mdio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/realtek,rtl9301-mdio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek RTL9300 MDIO Controller
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
15 - items:
16 - enum:
17 - realtek,rtl9302b-mdio
18 - realtek,rtl9302c-mdio
[all …]
H A Drealtek,rtl9301-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/realtek,rtl9301-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Realtek Switch with Internal CPU
10 - Chris Packham <chris.packham@alliedtelesis.co.nz>
17 $ref: ethernet-switch.yaml#/$defs/ethernet-ports
22 - enum:
23 - realtek,rtl9301-switch
24 - realtek,rtl9302b-switch
[all …]
/linux/arch/mips/boot/dts/realtek/
H A Drtl930x.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
4 compatible = "realtek,rtl9302-soc";
6 #address-cells = <1>;
7 #size-cells = <1>;
15 compatible = "mti,cpu-interrupt-controller";
16 #address-cells = <0>;
17 #interrupt-cells = <1>;
18 interrupt-controller;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
/linux/drivers/net/dsa/realtek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "Realtek Ethernet switch family support"
10 Select to enable support for Realtek Ethernet switch chips.
19 bool "Realtek MDIO interface support"
23 through MDIO.
26 bool "Realtek SMI interface support"
33 tristate "Realtek RTL8365MB switch driver"
37 Select to enable support for Realtek RTL8365MB-VC and RTL8367S.
40 tristate "Realtek RTL8366RB switch driver"
44 Select to enable support for Realtek RTL8366RB.
H A Drtl83xx.c1 // SPDX-License-Identifier: GPL-2.0+
7 #include "realtek.h"
11 * rtl83xx_lock() - Locks the mutex used by regmaps
19 * Context: Can sleep. Holds priv->map_lock lock.
26 mutex_lock(&priv->map_lock); in rtl83xx_lock()
31 * rtl83xx_unlock() - Unlocks the mutex used by regmaps
36 * Context: Releases priv->map_lock lock.
43 mutex_unlock(&priv->map_lock); in rtl83xx_unlock()
49 struct realtek_priv *priv = bus->priv; in rtl83xx_user_mdio_read()
51 return priv->ops->phy_read(priv, addr, regnum); in rtl83xx_user_mdio_read()
[all …]
H A Drealtek-smi.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek Simple Management Interface (SMI) driver
5 * The SMI protocol piggy-backs the MDIO MDC and MDIO signals levels
6 * but the protocol is not MDIO at all. Instead it is a Realtek
7 * pecularity that need to bit-bang the lines in a special way to
12 * RTL8366 - The original version, apparently
13 * RTL8369 - Similar enough to have the same datsheet as RTL8366
14 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
16 * RTL8366S - Is this "RTL8366 super"?
17 * RTL8367 - Has an OpenWRT driver as well
[all …]
H A Drealtek-mdio.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Realtek MDIO interface driver
6 * RTL8366 - The original version, apparently
7 * RTL8369 - Similar enough to have the same datsheet as RTL8366
8 * RTL8366RB - Probably reads out "RTL8366 revision B", has a quite
10 * RTL8366S - Is this "RTL8366 super"?
11 * RTL8367 - Has an OpenWRT driver as well
12 * RTL8368S - Seems to be an alternative name for RTL8366RB
13 * RTL8370 - Also uses SMI
19 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_NET_DSA_REALTEK) += realtek_dsa.o
3 realtek_dsa-objs := rtl83xx.o
6 realtek_dsa-objs += realtek-mdio.o
10 realtek_dsa-objs += realtek-smi.o
13 obj-$(CONFIG_NET_DSA_REALTEK_RTL8366RB) += rtl8366.o
14 rtl8366-objs := rtl8366-core.o rtl8366rb.o
16 rtl8366-objs += rtl8366rb-leds.o
18 obj-$(CONFIG_NET_DSA_REALTEK_RTL8365MB) += rtl8365mb.o
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
10 * RGMII. The switch is configured via the Realtek Simple Management Interface
11 * (SMI), which uses the MDIO/MDC lines.
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm47094-asus-rt-ac88u.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "bcm47094-asus-rt-ac3100.dtsi"
11 compatible = "asus,rt-ac88u", "brcm,bcm47094", "brcm,bcm4708";
12 model = "ASUS RT-AC88U";
16 #nvmem-cell-cells = <1>;
21 compatible = "realtek,rtl8365mb";
22 mdc-gpios = <&chipcommon 6 GPIO_ACTIVE_HIGH>;
23 mdio-gpios = <&chipcommon 7 GPIO_ACTIVE_HIGH>;
24 reset-gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
[all …]
/linux/drivers/net/mdio/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 # Makefile for Linux MDIO bus drivers
4 obj-$(CONFIG_ACPI_MDIO) += acpi_mdio.o
5 obj-$(CONFIG_FWNODE_MDIO) += fwnode_mdio.o
6 obj-$(CONFIG_OF_MDIO) += of_mdio.o
8 obj-$(CONFIG_MDIO_AIROHA) += mdio-airoha.o
9 obj-$(CONFIG_MDIO_ASPEED) += mdio-aspeed.o
10 obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
11 obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
12 obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini-dlink-dir-685.dts2 * Device Tree file for D-Link DIR-685 Xtreme N Storage Router
5 /dts-v1/;
8 #include <dt-bindings/input/input.h>
11 model = "D-Link DIR-685 Xtreme N Storage Router";
12 compatible = "dlink,dir-685", "cortina,gemini";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 /* 128 MB SDRAM in 2 x Hynix HY5DU121622DTP-D43 */
24 stdout-path = "uart0:19200n8";
28 compatible = "gpio-keys";
[all …]
H A Dgemini-dlink-dns-313.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree file for D-Link DNS-313 1-Bay Network Storage Enclosure
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/thermal/thermal.h>
13 model = "D-Link DNS-313 1-Bay Network Storage Enclosure";
14 compatible = "dlink,dns-313", "cortina,gemini";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 /* 64 MB SDRAM in a Nanya NT5DS32M16BS-6K package */
[all …]
/linux/drivers/net/phy/realtek/
H A Drealtek_main.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* drivers/net/phy/realtek.c
4 * Driver for Realtek PHYs
20 #include "realtek.h"
125 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
126 * is set, they cannot be accessed by C45-over-C22.
164 MODULE_DESCRIPTION("Realtek PHY driver");
219 struct device *dev = &phydev->mdio.dev; in rtl821x_probe()
221 u32 phy_id = phydev->drv->phy_id; in rtl821x_probe()
226 return -ENOMEM; in rtl821x_probe()
[all …]
H A Drealtek_hwmon.c1 // SPDX-License-Identifier: GPL-2.0+
3 * HWMON support for Realtek PHY's
11 #include "realtek.h"
20 raw -= 1024; in rtl822x_hwmon_get_temp()
42 return -EINVAL; in rtl822x_hwmon_read()
65 struct device *hwdev, *dev = &phydev->mdio.dev; in rtl822x_hwmon_init()
67 /* Ensure over-temp alarm is reset. */ in rtl822x_hwmon_init()
/linux/arch/mips/boot/dts/loongson/
H A Dlsgz_1b_dev.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "loongson,lsgz-1b-dev", "loongson,ls1b";
31 stdout-path = "serial0:115200n8";
35 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
46 linux,default-trigger = "nand-disk";
50 codec: audio-codec {
[all …]
H A Dls1b-demo.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2023-2025 Keguang Zhang <keguang.zhang@gmail.com>
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
13 compatible = "loongson,ls1b-demo", "loongson,ls1b";
14 model = "LS1B-DEMO Board";
30 stdout-path = "serial0:38400n8";
33 codec: audio-codec {
34 compatible = "realtek,alc203";
35 #sound-dai-cells = <0>;
[all …]
/linux/arch/arm/boot/dts/st/
H A Dstm32mp135f-dhcor-dhsbc.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
6 * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG
7 * DHCOR PCB number: 718-100 or newer
8 * DHSBC PCB number: 719-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/regulator/st,stm32mp13-regulator.h>
16 #include "stm32mp13xx-dhcor-som.dtsi"
20 compatible = "dh,stm32mp135f-dhcor-dhsbc",
21 "dh,stm32mp135f-dhcor-som",
32 stdout-path = "serial0:115200n8";
[all …]
/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm018-dc4.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
16 model = "ZynqMP zc1751-xm018-dc4";
17 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
34 stdout-path = "serial0:115200n8";
117 phy-mode = "rgmii-id";
118 phy-handle = <&ethernet_phy0>;
[all …]
/linux/arch/arm/boot/dts/amlogic/
H A Dmeson8b-ec100.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
22 stdout-path = "serial0:115200n8";
30 emmc_pwrseq: emmc-pwrseq {
31 compatible = "mmc-pwrseq-emmc";
32 reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
35 gpio-keys {
36 compatible = "gpio-keys-polled";
[all …]
H A Dmeson8-fernsehfee3.dts1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/linux-event-codes.h>
8 #include <dt-bindings/leds/common.h>
27 stdout-path = "serial0:115200n8";
35 gpio-keys {
36 compatible = "gpio-keys-polled";
37 poll-interval = <100>;
39 power-button {
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-debix-som-a-bmb-08.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
22 stdout-path = &uart2;
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368-lba3368.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/clock/rockchip,rk808.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/sound/rt5640.h>
25 stdout-path = "serial1:115200n8";
33 adc-key {
34 compatible = "adc-keys";
35 io-channels = <&saradc 1>;
[all …]
/linux/drivers/net/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
7 tristate "MDIO bus consumer layer"
9 MDIO bus consumer layer
40 Adds support for a set of LED trigger events per-PHY. Link
44 logical-or of all the link speed ones.
63 tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
66 Adds the platform "fixed" MDIO Bus to cover the boards that use
67 PHYs that are not connected to the real MDIO bus.
69 Currently tested with mpc866ads and mpc8349e-mitx.
121 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
[all …]
/linux/drivers/staging/rtl8723bs/include/
H A Drtl8723b_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
10 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
81 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
82 #define REG_MDIO_RDATA_8723B 0x0356 /* MDIO for Reads PCIE PHY */
83 #define REG_MDIO_CTL_8723B 0x0358 /* MDIO for Control */
87 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
190 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
216 /* IMR DW1(0x00B4-00B7) Bit 0-31 */

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