xref: /linux/Documentation/devicetree/bindings/net/realtek,rtl9301-switch.yaml (revision 1a9239bb4253f9076b5b4b2a1a4e8d7defd77a95)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/realtek,rtl9301-switch.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Realtek Switch with Internal CPU
8
9maintainers:
10  - Chris Packham <chris.packham@alliedtelesis.co.nz>
11
12description:
13  The RTL9300 is a series of is an Ethernet switches with an integrated CPU. A
14  number of different peripherals are accessed through a common register block,
15  represented here as a syscon node.
16
17$ref: ethernet-switch.yaml#/$defs/ethernet-ports
18
19properties:
20  compatible:
21    items:
22      - enum:
23          - realtek,rtl9301-switch
24          - realtek,rtl9302b-switch
25          - realtek,rtl9302c-switch
26          - realtek,rtl9303-switch
27      - const: syscon
28      - const: simple-mfd
29
30  reg:
31    maxItems: 1
32
33  interrupts:
34    maxItems: 2
35
36  interrupt-names:
37    items:
38      - const: switch
39      - const: nic
40
41  '#address-cells':
42    const: 1
43
44  '#size-cells':
45    const: 1
46
47  ethernet-ports:
48    type: object
49
50patternProperties:
51  'reboot@[0-9a-f]+$':
52    $ref: /schemas/power/reset/syscon-reboot.yaml#
53
54  'i2c@[0-9a-f]+$':
55    $ref: /schemas/i2c/realtek,rtl9301-i2c.yaml#
56
57  'mdio-controller@[0-9a-f]+$':
58    $ref: realtek,rtl9301-mdio.yaml#
59
60required:
61  - compatible
62  - reg
63  - interrupts
64  - interrupt-names
65
66additionalProperties: false
67
68examples:
69  - |
70    ethernet-switch@1b000000 {
71      compatible = "realtek,rtl9301-switch", "syscon", "simple-mfd";
72      reg = <0x1b000000 0x10000>;
73      interrupt-parent = <&intc>;
74      interrupts = <23>, <24>;
75      interrupt-names = "switch", "nic";
76      #address-cells = <1>;
77      #size-cells = <1>;
78
79      reboot@c {
80        compatible = "syscon-reboot";
81        reg = <0x0c 0x4>;
82        value = <0x01>;
83      };
84
85      i2c@36c {
86        compatible = "realtek,rtl9301-i2c";
87        reg = <0x36c 0x14>;
88        #address-cells = <1>;
89        #size-cells = <0>;
90
91        i2c@0 {
92          reg = <0>;
93          #address-cells = <1>;
94          #size-cells = <0>;
95          gpio@20 {
96            compatible = "nxp,pca9555";
97            gpio-controller;
98            #gpio-cells = <2>;
99            reg = <0x20>;
100          };
101        };
102
103        i2c@2 {
104          reg = <2>;
105          #address-cells = <1>;
106          #size-cells = <0>;
107          gpio@20 {
108            compatible = "nxp,pca9555";
109            gpio-controller;
110            #gpio-cells = <2>;
111            reg = <0x20>;
112          };
113        };
114      };
115
116      i2c@388 {
117        compatible = "realtek,rtl9301-i2c";
118        reg = <0x388 0x14>;
119        #address-cells = <1>;
120        #size-cells = <0>;
121
122        i2c@7 {
123          reg = <7>;
124          #address-cells = <1>;
125          #size-cells = <0>;
126          gpio@20 {
127            compatible = "nxp,pca9555";
128            gpio-controller;
129            #gpio-cells = <2>;
130            reg = <0x20>;
131          };
132        };
133      };
134
135      mdio-controller@ca00 {
136        compatible = "realtek,rtl9301-mdio";
137        reg = <0xca00 0x200>;
138        #address-cells = <1>;
139        #size-cells = <0>;
140
141        mdio-bus@0 {
142          reg = <0>;
143          #address-cells = <1>;
144          #size-cells = <0>;
145
146          phy1: ethernet-phy@0 {
147            reg = <0>;
148          };
149        };
150        mdio-bus@1 {
151          reg = <1>;
152          #address-cells = <1>;
153          #size-cells = <0>;
154
155          phy2: ethernet-phy@0 {
156            reg = <0>;
157          };
158        };
159      };
160
161      ethernet-ports {
162        #address-cells = <1>;
163        #size-cells = <0>;
164
165        port@0 {
166          reg = <0>;
167          phy-handle = <&phy1>;
168        };
169        port@1 {
170          reg = <1>;
171          phy-handle = <&phy2>;
172        };
173      };
174    };
175
176