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Searched +full:r8a7795 +full:- +full:rst (Results 1 – 12 of 12) sorted by relevance

/linux/Documentation/devicetree/bindings/reset/
H A Drenesas,rst.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/renesas,rst.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car and RZ/G Reset Controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Magnus Damm <magnus.damm@gmail.com>
14 The R-Car and RZ/G Reset Controllers provide reset control, and implement the
16 - Latching of the levels on mode pins when PRESET# is negated,
17 - Mode monitoring register,
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/linux/drivers/soc/renesas/
H A Drcar-rst.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen1 RESET/WDT, R-Car Gen2, Gen3, and RZ/G RST Driver
11 #include <linux/soc/renesas/rcar-rst.h>
38 * Most of the R-Car Gen3 SoCs have an ARM Realtime Core.
47 return -EINVAL; in rcar_rst_set_gen3_rproc_boot_addr()
87 /* RZ/G1 is handled like R-Car Gen2 */
88 { .compatible = "renesas,r8a7742-rst", .data = &rcar_rst_gen2 },
89 { .compatible = "renesas,r8a7743-rst", .data = &rcar_rst_gen2 },
90 { .compatible = "renesas,r8a7744-rst", .data = &rcar_rst_gen2 },
91 { .compatible = "renesas,r8a7745-rst", .data = &rcar_rst_gen2 },
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/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
18 compatible = "renesas,r8a7795";
19 #address-cells = <2>;
20 #size-cells = <2>;
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
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/linux/drivers/clk/renesas/
H A Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7795 Clock Pulse Generator / Module Standby and Software Reset
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
133 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
134 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
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H A Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
136 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
137 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
138 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
139 DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
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H A Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-cpg-lib.h"
22 #include "rcar-gen3-cpg.h"
125 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
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H A Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
129 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
130 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
139 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
140 DEF_MOD("intc-ap", 408, R8A77980_CLK_S0D3),
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H A Dr8a779a0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
15 #include <linux/clk-provider.h>
20 #include <linux/soc/renesas/rcar-rst.h>
22 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
24 #include "renesas-cpg-mssr.h"
25 #include "rcar-gen4-cpg.h"
179 DEF_MOD("rpc-if", 629, R8A779A0_CLK_RPCD2),
185 DEF_MOD("sys-dmac1", 709, R8A779A0_CLK_S1D2),
186 DEF_MOD("sys-dmac2", 710, R8A779A0_CLK_S1D2),
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H A Dr8a77990-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
150 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
151 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
152 DEF_MOD("sys-dmac0", 219, R8A77990_CLK_S3D1),
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H A Dr8a774e1-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
15 #include <linux/soc/renesas/rcar-rst.h>
17 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
19 #include "renesas-cpg-mssr.h"
20 #include "rcar-gen3-cpg.h"
129 DEF_MOD("fdp1-1", 118, R8A774E1_CLK_S0D1),
130 DEF_MOD("fdp1-0", 119, R8A774E1_CLK_S0D1),
147 DEF_MOD("sys-dmac2", 217, R8A774E1_CLK_S3D1),
148 DEF_MOD("sys-dmac1", 218, R8A774E1_CLK_S3D1),
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H A Dr8a77965-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
17 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
130 DEF_MOD("fdp1-0", 119, R8A77965_CLK_S0D1),
145 DEF_MOD("sys-dmac2", 217, R8A77965_CLK_S3D1),
146 DEF_MOD("sys-dmac1", 218, R8A77965_CLK_S3D1),
147 DEF_MOD("sys-dmac0", 219, R8A77965_CLK_S0D3),
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H A Dr8a7796-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
3 * r8a7796 (R-Car M3-W/W+) Clock Pulse Generator / Module Standby and Software
6 * Copyright (C) 2016-2019 Glider bvba
7 * Copyright (C) 2018-2019 Renesas Electronics Corp.
9 * Based on r8a7795-cpg-mssr.c
19 #include <linux/soc/renesas/rcar-rst.h>
21 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen3-cpg.h"
135 DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1),
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