19e288cefSKuninori Morimoto // SPDX-License-Identifier: GPL-2.0
28d46e28fSSergei Shtylyov /*
38d46e28fSSergei Shtylyov * r8a77970 Clock Pulse Generator / Module Standby and Software Reset
48d46e28fSSergei Shtylyov *
5381081ffSSergei Shtylyov * Copyright (C) 2017-2018 Cogent Embedded Inc.
68d46e28fSSergei Shtylyov *
78d46e28fSSergei Shtylyov * Based on r8a7795-cpg-mssr.c
88d46e28fSSergei Shtylyov *
98d46e28fSSergei Shtylyov * Copyright (C) 2015 Glider bvba
108d46e28fSSergei Shtylyov */
118d46e28fSSergei Shtylyov
12381081ffSSergei Shtylyov #include <linux/clk-provider.h>
138d46e28fSSergei Shtylyov #include <linux/device.h>
148d46e28fSSergei Shtylyov #include <linux/init.h>
158d46e28fSSergei Shtylyov #include <linux/kernel.h>
168d46e28fSSergei Shtylyov #include <linux/soc/renesas/rcar-rst.h>
178d46e28fSSergei Shtylyov
188d46e28fSSergei Shtylyov #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
198d46e28fSSergei Shtylyov
208d46e28fSSergei Shtylyov #include "renesas-cpg-mssr.h"
21*c001f9c9SGeert Uytterhoeven #include "rcar-cpg-lib.h"
228d46e28fSSergei Shtylyov #include "rcar-gen3-cpg.h"
238d46e28fSSergei Shtylyov
24381081ffSSergei Shtylyov #define CPG_SD0CKCR 0x0074
25381081ffSSergei Shtylyov
26381081ffSSergei Shtylyov enum r8a77970_clk_types {
27381081ffSSergei Shtylyov CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
28381081ffSSergei Shtylyov CLK_TYPE_R8A77970_SD0,
29381081ffSSergei Shtylyov };
30381081ffSSergei Shtylyov
318d46e28fSSergei Shtylyov enum clk_ids {
328d46e28fSSergei Shtylyov /* Core Clock Outputs exported to DT */
338d46e28fSSergei Shtylyov LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
348d46e28fSSergei Shtylyov
358d46e28fSSergei Shtylyov /* External Input Clocks */
368d46e28fSSergei Shtylyov CLK_EXTAL,
378d46e28fSSergei Shtylyov CLK_EXTALR,
388d46e28fSSergei Shtylyov
398d46e28fSSergei Shtylyov /* Internal Core Clocks */
408d46e28fSSergei Shtylyov CLK_MAIN,
418d46e28fSSergei Shtylyov CLK_PLL0,
428d46e28fSSergei Shtylyov CLK_PLL1,
438d46e28fSSergei Shtylyov CLK_PLL3,
448d46e28fSSergei Shtylyov CLK_PLL1_DIV2,
458d46e28fSSergei Shtylyov CLK_PLL1_DIV4,
468d46e28fSSergei Shtylyov
478d46e28fSSergei Shtylyov /* Module Clocks */
488d46e28fSSergei Shtylyov MOD_CLK_BASE
498d46e28fSSergei Shtylyov };
508d46e28fSSergei Shtylyov
51381081ffSSergei Shtylyov static const struct clk_div_table cpg_sd0h_div_table[] = {
52381081ffSSergei Shtylyov { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 },
53381081ffSSergei Shtylyov { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
54381081ffSSergei Shtylyov { 8, 24 }, { 10, 36 }, { 11, 48 }, { 0, 0 },
55381081ffSSergei Shtylyov };
56381081ffSSergei Shtylyov
57381081ffSSergei Shtylyov static const struct clk_div_table cpg_sd0_div_table[] = {
58381081ffSSergei Shtylyov { 4, 8 }, { 5, 12 }, { 6, 16 }, { 7, 18 },
59381081ffSSergei Shtylyov { 8, 24 }, { 10, 36 }, { 11, 48 }, { 12, 10 },
60381081ffSSergei Shtylyov { 0, 0 },
61381081ffSSergei Shtylyov };
62381081ffSSergei Shtylyov
638d46e28fSSergei Shtylyov static const struct cpg_core_clk r8a77970_core_clks[] __initconst = {
648d46e28fSSergei Shtylyov /* External Clock Inputs */
658d46e28fSSergei Shtylyov DEF_INPUT("extal", CLK_EXTAL),
668d46e28fSSergei Shtylyov DEF_INPUT("extalr", CLK_EXTALR),
678d46e28fSSergei Shtylyov
688d46e28fSSergei Shtylyov /* Internal Core Clocks */
698d46e28fSSergei Shtylyov DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
708d46e28fSSergei Shtylyov DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
718d46e28fSSergei Shtylyov DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
728d46e28fSSergei Shtylyov DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
738d46e28fSSergei Shtylyov
748d46e28fSSergei Shtylyov DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
758d46e28fSSergei Shtylyov DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
768d46e28fSSergei Shtylyov
778d46e28fSSergei Shtylyov /* Core Clock Outputs */
7888ddf98aSGeert Uytterhoeven DEF_FIXED("z2", R8A77970_CLK_Z2, CLK_PLL1_DIV4, 1, 1),
798d46e28fSSergei Shtylyov DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
808d46e28fSSergei Shtylyov DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
818d46e28fSSergei Shtylyov DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
828d46e28fSSergei Shtylyov DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
838d46e28fSSergei Shtylyov DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
848d46e28fSSergei Shtylyov DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
858d46e28fSSergei Shtylyov DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
868d46e28fSSergei Shtylyov DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
878d46e28fSSergei Shtylyov DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
888d46e28fSSergei Shtylyov DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
898d46e28fSSergei Shtylyov
90381081ffSSergei Shtylyov DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
91381081ffSSergei Shtylyov CLK_PLL1_DIV2),
92381081ffSSergei Shtylyov DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
93381081ffSSergei Shtylyov
946f44610cSSergei Shtylyov DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
956f44610cSSergei Shtylyov DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
966f44610cSSergei Shtylyov
978d46e28fSSergei Shtylyov DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
988d46e28fSSergei Shtylyov DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
99396bc9d4SGeert Uytterhoeven DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
1008d46e28fSSergei Shtylyov
1018d46e28fSSergei Shtylyov DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
1028d46e28fSSergei Shtylyov DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
1038d46e28fSSergei Shtylyov DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
1048d46e28fSSergei Shtylyov
1058d46e28fSSergei Shtylyov DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
1068d46e28fSSergei Shtylyov DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
1078d46e28fSSergei Shtylyov };
1088d46e28fSSergei Shtylyov
1098d46e28fSSergei Shtylyov static const struct mssr_mod_clk r8a77970_mod_clks[] __initconst = {
1106207ba04SSergei Shtylyov DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
1116207ba04SSergei Shtylyov DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
1126207ba04SSergei Shtylyov DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
1136207ba04SSergei Shtylyov DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
1146207ba04SSergei Shtylyov DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
1158d46e28fSSergei Shtylyov DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
1168d46e28fSSergei Shtylyov DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
1178d46e28fSSergei Shtylyov DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
1188d46e28fSSergei Shtylyov DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
1198d46e28fSSergei Shtylyov DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
1208d46e28fSSergei Shtylyov DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
1218d46e28fSSergei Shtylyov DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
1228d46e28fSSergei Shtylyov DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
1238d46e28fSSergei Shtylyov DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
1248d46e28fSSergei Shtylyov DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
1258d46e28fSSergei Shtylyov DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
1268d46e28fSSergei Shtylyov DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
1275986b503SSergei Shtylyov DEF_MOD("cmt3", 300, R8A77970_CLK_R),
1285986b503SSergei Shtylyov DEF_MOD("cmt2", 301, R8A77970_CLK_R),
1295986b503SSergei Shtylyov DEF_MOD("cmt1", 302, R8A77970_CLK_R),
1305986b503SSergei Shtylyov DEF_MOD("cmt0", 303, R8A77970_CLK_R),
1319ef5e037SSergei Shtylyov DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
132381081ffSSergei Shtylyov DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
1338d46e28fSSergei Shtylyov DEF_MOD("rwdt", 402, R8A77970_CLK_R),
1348d46e28fSSergei Shtylyov DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
1358d46e28fSSergei Shtylyov DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
1368d46e28fSSergei Shtylyov DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
1378d46e28fSSergei Shtylyov DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
1388d46e28fSSergei Shtylyov DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
1398d46e28fSSergei Shtylyov DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
1408d46e28fSSergei Shtylyov DEF_MOD("thermal", 522, R8A77970_CLK_CP),
1418d46e28fSSergei Shtylyov DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
1428d46e28fSSergei Shtylyov DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
1438d46e28fSSergei Shtylyov DEF_MOD("vspd0", 623, R8A77970_CLK_S2D1),
1448d46e28fSSergei Shtylyov DEF_MOD("csi40", 716, R8A77970_CLK_CSI0),
1458d46e28fSSergei Shtylyov DEF_MOD("du0", 724, R8A77970_CLK_S2D1),
14664082568SSergei Shtylyov DEF_MOD("lvds", 727, R8A77970_CLK_S2D1),
1478d46e28fSSergei Shtylyov DEF_MOD("vin3", 808, R8A77970_CLK_S2D1),
1488d46e28fSSergei Shtylyov DEF_MOD("vin2", 809, R8A77970_CLK_S2D1),
1498d46e28fSSergei Shtylyov DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
1508d46e28fSSergei Shtylyov DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
1518d46e28fSSergei Shtylyov DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
1528d46e28fSSergei Shtylyov DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
1538d46e28fSSergei Shtylyov DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
1548d46e28fSSergei Shtylyov DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
1558d46e28fSSergei Shtylyov DEF_MOD("gpio2", 910, R8A77970_CLK_CP),
1568d46e28fSSergei Shtylyov DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
1578d46e28fSSergei Shtylyov DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
1588d46e28fSSergei Shtylyov DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
1596f44610cSSergei Shtylyov DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
1608d46e28fSSergei Shtylyov DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
1618d46e28fSSergei Shtylyov DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
1628d46e28fSSergei Shtylyov DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
1638d46e28fSSergei Shtylyov DEF_MOD("i2c1", 930, R8A77970_CLK_S2D2),
1648d46e28fSSergei Shtylyov DEF_MOD("i2c0", 931, R8A77970_CLK_S2D2),
1658d46e28fSSergei Shtylyov };
1668d46e28fSSergei Shtylyov
1678d46e28fSSergei Shtylyov static const unsigned int r8a77970_crit_mod_clks[] __initconst = {
168f23f1101SUlrich Hecht MOD_CLK_ID(402), /* RWDT */
1698d46e28fSSergei Shtylyov MOD_CLK_ID(408), /* INTC-AP (GIC) */
1708d46e28fSSergei Shtylyov };
1718d46e28fSSergei Shtylyov
1728d46e28fSSergei Shtylyov /*
1738d46e28fSSergei Shtylyov * CPG Clock Data
1748d46e28fSSergei Shtylyov */
1758d46e28fSSergei Shtylyov
1768d46e28fSSergei Shtylyov /*
1778d46e28fSSergei Shtylyov * MD EXTAL PLL0 PLL1 PLL3
1788d46e28fSSergei Shtylyov * 14 13 19 (MHz)
1798d46e28fSSergei Shtylyov *-------------------------------------------------
1808d46e28fSSergei Shtylyov * 0 0 0 16.66 x 1 x192 x192 x96
1818d46e28fSSergei Shtylyov * 0 0 1 16.66 x 1 x192 x192 x80
1828d46e28fSSergei Shtylyov * 0 1 0 20 x 1 x160 x160 x80
1838d46e28fSSergei Shtylyov * 0 1 1 20 x 1 x160 x160 x66
1848d46e28fSSergei Shtylyov * 1 0 0 27 / 2 x236 x236 x118
1858d46e28fSSergei Shtylyov * 1 0 1 27 / 2 x236 x236 x98
1868d46e28fSSergei Shtylyov * 1 1 0 33.33 / 2 x192 x192 x96
1878d46e28fSSergei Shtylyov * 1 1 1 33.33 / 2 x192 x192 x80
1888d46e28fSSergei Shtylyov */
1898d46e28fSSergei Shtylyov #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
1908d46e28fSSergei Shtylyov (((md) & BIT(13)) >> 12) | \
1918d46e28fSSergei Shtylyov (((md) & BIT(19)) >> 19))
1928d46e28fSSergei Shtylyov
1938d46e28fSSergei Shtylyov static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[8] __initconst = {
1948d46e28fSSergei Shtylyov /* EXTAL div PLL1 mult/div PLL3 mult/div */
1958d46e28fSSergei Shtylyov { 1, 192, 1, 96, 1, },
1968d46e28fSSergei Shtylyov { 1, 192, 1, 80, 1, },
1978d46e28fSSergei Shtylyov { 1, 160, 1, 80, 1, },
1988d46e28fSSergei Shtylyov { 1, 160, 1, 66, 1, },
1998d46e28fSSergei Shtylyov { 2, 236, 1, 118, 1, },
2008d46e28fSSergei Shtylyov { 2, 236, 1, 98, 1, },
2018d46e28fSSergei Shtylyov { 2, 192, 1, 96, 1, },
2028d46e28fSSergei Shtylyov { 2, 192, 1, 80, 1, },
2038d46e28fSSergei Shtylyov };
2048d46e28fSSergei Shtylyov
r8a77970_cpg_mssr_init(struct device * dev)2058d46e28fSSergei Shtylyov static int __init r8a77970_cpg_mssr_init(struct device *dev)
2068d46e28fSSergei Shtylyov {
2078d46e28fSSergei Shtylyov const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
2088d46e28fSSergei Shtylyov u32 cpg_mode;
2098d46e28fSSergei Shtylyov int error;
2108d46e28fSSergei Shtylyov
2118d46e28fSSergei Shtylyov error = rcar_rst_read_mode_pins(&cpg_mode);
2128d46e28fSSergei Shtylyov if (error)
2138d46e28fSSergei Shtylyov return error;
2148d46e28fSSergei Shtylyov
2158d46e28fSSergei Shtylyov cpg_pll_config = &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
2168d46e28fSSergei Shtylyov
2178d46e28fSSergei Shtylyov return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode);
2188d46e28fSSergei Shtylyov }
2198d46e28fSSergei Shtylyov
r8a77970_cpg_clk_register(struct device * dev,const struct cpg_core_clk * core,const struct cpg_mssr_info * info,struct clk ** clks,void __iomem * base,struct raw_notifier_head * notifiers)220381081ffSSergei Shtylyov static struct clk * __init r8a77970_cpg_clk_register(struct device *dev,
221381081ffSSergei Shtylyov const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
222381081ffSSergei Shtylyov struct clk **clks, void __iomem *base,
223381081ffSSergei Shtylyov struct raw_notifier_head *notifiers)
224381081ffSSergei Shtylyov {
225381081ffSSergei Shtylyov const struct clk_div_table *table;
226381081ffSSergei Shtylyov const struct clk *parent;
227381081ffSSergei Shtylyov unsigned int shift;
228381081ffSSergei Shtylyov
229381081ffSSergei Shtylyov switch (core->type) {
230381081ffSSergei Shtylyov case CLK_TYPE_R8A77970_SD0H:
231381081ffSSergei Shtylyov table = cpg_sd0h_div_table;
232381081ffSSergei Shtylyov shift = 8;
233381081ffSSergei Shtylyov break;
234381081ffSSergei Shtylyov case CLK_TYPE_R8A77970_SD0:
235381081ffSSergei Shtylyov table = cpg_sd0_div_table;
236381081ffSSergei Shtylyov shift = 4;
237381081ffSSergei Shtylyov break;
238381081ffSSergei Shtylyov default:
239381081ffSSergei Shtylyov return rcar_gen3_cpg_clk_register(dev, core, info, clks, base,
240381081ffSSergei Shtylyov notifiers);
241381081ffSSergei Shtylyov }
242381081ffSSergei Shtylyov
243381081ffSSergei Shtylyov parent = clks[core->parent];
244381081ffSSergei Shtylyov if (IS_ERR(parent))
245381081ffSSergei Shtylyov return ERR_CAST(parent);
246381081ffSSergei Shtylyov
247381081ffSSergei Shtylyov return clk_register_divider_table(NULL, core->name,
248381081ffSSergei Shtylyov __clk_get_name(parent), 0,
249381081ffSSergei Shtylyov base + CPG_SD0CKCR,
250381081ffSSergei Shtylyov shift, 4, 0, table, &cpg_lock);
251381081ffSSergei Shtylyov }
252381081ffSSergei Shtylyov
2538d46e28fSSergei Shtylyov const struct cpg_mssr_info r8a77970_cpg_mssr_info __initconst = {
2548d46e28fSSergei Shtylyov /* Core Clocks */
2558d46e28fSSergei Shtylyov .core_clks = r8a77970_core_clks,
2568d46e28fSSergei Shtylyov .num_core_clks = ARRAY_SIZE(r8a77970_core_clks),
2578d46e28fSSergei Shtylyov .last_dt_core_clk = LAST_DT_CORE_CLK,
2588d46e28fSSergei Shtylyov .num_total_core_clks = MOD_CLK_BASE,
2598d46e28fSSergei Shtylyov
2608d46e28fSSergei Shtylyov /* Module Clocks */
2618d46e28fSSergei Shtylyov .mod_clks = r8a77970_mod_clks,
2628d46e28fSSergei Shtylyov .num_mod_clks = ARRAY_SIZE(r8a77970_mod_clks),
2638d46e28fSSergei Shtylyov .num_hw_mod_clks = 12 * 32,
2648d46e28fSSergei Shtylyov
2658d46e28fSSergei Shtylyov /* Critical Module Clocks */
2668d46e28fSSergei Shtylyov .crit_mod_clks = r8a77970_crit_mod_clks,
2678d46e28fSSergei Shtylyov .num_crit_mod_clks = ARRAY_SIZE(r8a77970_crit_mod_clks),
2688d46e28fSSergei Shtylyov
2698d46e28fSSergei Shtylyov /* Callbacks */
2708d46e28fSSergei Shtylyov .init = r8a77970_cpg_mssr_init,
271381081ffSSergei Shtylyov .cpg_clk_register = r8a77970_cpg_clk_register,
2728d46e28fSSergei Shtylyov };
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