Searched full:queue0 (Results 1 – 19 of 19) sorted by relevance
146 queue = pio->queue0; in parse_cookie()402 b43legacy_destroy_pioqueue(pio->queue0); in b43legacy_pio_free()403 pio->queue0 = NULL; in b43legacy_pio_free()415 pio->queue0 = queue; in b43legacy_pio_init()447 b43legacy_destroy_pioqueue(pio->queue0); in b43legacy_pio_init()448 pio->queue0 = NULL; in b43legacy_pio_init()657 pio->queue0->tx_frozen = 1; in b43legacy_pio_freeze_txqueues()669 pio->queue0->tx_frozen = 0; in b43legacy_pio_thaw_txqueues()673 if (!list_empty(&pio->queue0->txqueue)) in b43legacy_pio_thaw_txqueues()674 tasklet_schedule(&pio->queue0->txtask); in b43legacy_pio_thaw_txqueues()
538 struct b43legacy_pioqueue *queue0; member
1352 b43legacy_pio_rx(dev->pio.queue0); in b43legacy_interrupt_tasklet()
76 queue0 {};82 queue0 {};
101 queue0 {};106 queue0 {};
77 queue0 {93 queue0 {
304 queue0 {332 queue0 {
37 - const: qdma-queue0125 interrupt-names = "qdma-error", "qdma-queue0", "qdma-queue1";
321 queue0 {};326 queue0 {};
567 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */587 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */618 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */640 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */685 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */692 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */736 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
358 queue0 {};370 queue0 {};
703 queue0 {713 queue0 {
998 interrupt-names = "qdma-error", "qdma-queue0",
466 #define FM_SPCEPDA0 0x0200 /* parity/coding error: asyn. queue0 */
177 /* Policy: use pipe1 queue0 as high priority graphics queue if we in amdgpu_gfx_is_high_priority_graphics_queue()
4734 /* set the queue register mapping once for all: queue0 has a special in macb_init_dflt()4753 /* queue0 uses legacy registers */ in macb_init_dflt()
6666 "Enabling CBS on queue1 before queue0\n"); in igc_save_cbs_params()6672 "Disabling CBS on queue0 before queue1\n"); in igc_save_cbs_params()
1701 * Queue0 QueueMode must be set to 1b when in igb_config_tx_modes()