1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2N SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */ 13#define RZV2N_P0 0 14#define RZV2N_P1 1 15#define RZV2N_P2 2 16#define RZV2N_P3 3 17#define RZV2N_P4 4 18#define RZV2N_P5 5 19#define RZV2N_P6 6 20#define RZV2N_P7 7 21#define RZV2N_P8 8 22#define RZV2N_P9 9 23#define RZV2N_PA 10 24#define RZV2N_PB 11 25 26#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) 27#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) 28 29/ { 30 compatible = "renesas,r9a09g056"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 34 audio_extal_clk: audio-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 /* This value must be overridden by the board */ 38 clock-frequency = <0>; 39 }; 40 41 /* 42 * The default cluster table is based on the assumption that the PLLCA55 clock 43 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 44 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 45 * clocked to 1.8GHz as well). The table below should be overridden in the board 46 * DTS based on the PLLCA55 clock frequency. 47 */ 48 cluster0_opp: opp-table-0 { 49 compatible = "operating-points-v2"; 50 51 opp-1700000000 { 52 opp-hz = /bits/ 64 <1700000000>; 53 opp-microvolt = <900000>; 54 clock-latency-ns = <300000>; 55 }; 56 opp-850000000 { 57 opp-hz = /bits/ 64 <850000000>; 58 opp-microvolt = <800000>; 59 clock-latency-ns = <300000>; 60 }; 61 opp-425000000 { 62 opp-hz = /bits/ 64 <425000000>; 63 opp-microvolt = <800000>; 64 clock-latency-ns = <300000>; 65 }; 66 opp-212500000 { 67 opp-hz = /bits/ 64 <212500000>; 68 opp-microvolt = <800000>; 69 clock-latency-ns = <300000>; 70 opp-suspend; 71 }; 72 }; 73 74 cpus { 75 #address-cells = <1>; 76 #size-cells = <0>; 77 78 cpu0: cpu@0 { 79 compatible = "arm,cortex-a55"; 80 reg = <0>; 81 device_type = "cpu"; 82 next-level-cache = <&L3_CA55>; 83 enable-method = "psci"; 84 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; 85 operating-points-v2 = <&cluster0_opp>; 86 }; 87 88 cpu1: cpu@100 { 89 compatible = "arm,cortex-a55"; 90 reg = <0x100>; 91 device_type = "cpu"; 92 next-level-cache = <&L3_CA55>; 93 enable-method = "psci"; 94 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; 95 operating-points-v2 = <&cluster0_opp>; 96 }; 97 98 cpu2: cpu@200 { 99 compatible = "arm,cortex-a55"; 100 reg = <0x200>; 101 device_type = "cpu"; 102 next-level-cache = <&L3_CA55>; 103 enable-method = "psci"; 104 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; 105 operating-points-v2 = <&cluster0_opp>; 106 }; 107 108 cpu3: cpu@300 { 109 compatible = "arm,cortex-a55"; 110 reg = <0x300>; 111 device_type = "cpu"; 112 next-level-cache = <&L3_CA55>; 113 enable-method = "psci"; 114 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; 115 operating-points-v2 = <&cluster0_opp>; 116 }; 117 118 L3_CA55: cache-controller-0 { 119 compatible = "cache"; 120 cache-unified; 121 cache-size = <0x100000>; 122 cache-level = <3>; 123 }; 124 }; 125 126 psci { 127 compatible = "arm,psci-1.0", "arm,psci-0.2"; 128 method = "smc"; 129 }; 130 131 qextal_clk: qextal-clk { 132 compatible = "fixed-clock"; 133 #clock-cells = <0>; 134 /* This value must be overridden by the board */ 135 clock-frequency = <0>; 136 }; 137 138 rtxin_clk: rtxin-clk { 139 compatible = "fixed-clock"; 140 #clock-cells = <0>; 141 /* This value must be overridden by the board */ 142 clock-frequency = <0>; 143 }; 144 145 soc: soc { 146 compatible = "simple-bus"; 147 interrupt-parent = <&gic>; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 pinctrl: pinctrl@10410000 { 153 compatible = "renesas,r9a09g056-pinctrl"; 154 reg = <0 0x10410000 0 0x10000>; 155 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; 156 gpio-controller; 157 #gpio-cells = <2>; 158 gpio-ranges = <&pinctrl 0 0 96>; 159 power-domains = <&cpg>; 160 resets = <&cpg 0xa5>, <&cpg 0xa6>; 161 }; 162 163 cpg: clock-controller@10420000 { 164 compatible = "renesas,r9a09g056-cpg"; 165 reg = <0 0x10420000 0 0x10000>; 166 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 167 clock-names = "audio_extal", "rtxin", "qextal"; 168 #clock-cells = <2>; 169 #reset-cells = <1>; 170 #power-domain-cells = <0>; 171 }; 172 173 sys: system-controller@10430000 { 174 compatible = "renesas,r9a09g056-sys"; 175 reg = <0 0x10430000 0 0x10000>; 176 clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>; 177 resets = <&cpg 0x30>; 178 }; 179 180 scif: serial@11c01400 { 181 compatible = "renesas,scif-r9a09g056", 182 "renesas,scif-r9a09g057"; 183 reg = <0 0x11c01400 0 0x400>; 184 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 192 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 193 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 194 "tei", "tei-dri", "rxi-edge", "txi-edge"; 195 clocks = <&cpg CPG_MOD 0x8f>; 196 clock-names = "fck"; 197 power-domains = <&cpg>; 198 resets = <&cpg 0x95>; 199 status = "disabled"; 200 }; 201 202 gic: interrupt-controller@14900000 { 203 compatible = "arm,gic-v3"; 204 reg = <0x0 0x14900000 0 0x20000>, 205 <0x0 0x14940000 0 0x80000>; 206 #interrupt-cells = <3>; 207 #address-cells = <0>; 208 interrupt-controller; 209 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 210 }; 211 212 sdhi0: mmc@15c00000 { 213 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 214 reg = <0x0 0x15c00000 0 0x10000>; 215 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 218 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 219 clock-names = "core", "clkh", "cd", "aclk"; 220 resets = <&cpg 0xa7>; 221 power-domains = <&cpg>; 222 status = "disabled"; 223 224 sdhi0_vqmmc: vqmmc-regulator { 225 regulator-name = "SDHI0-VQMMC"; 226 regulator-min-microvolt = <1800000>; 227 regulator-max-microvolt = <3300000>; 228 status = "disabled"; 229 }; 230 }; 231 232 sdhi1: mmc@15c10000 { 233 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 234 reg = <0x0 0x15c10000 0 0x10000>; 235 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 238 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 239 clock-names = "core", "clkh", "cd", "aclk"; 240 resets = <&cpg 0xa8>; 241 power-domains = <&cpg>; 242 status = "disabled"; 243 244 sdhi1_vqmmc: vqmmc-regulator { 245 regulator-name = "SDHI1-VQMMC"; 246 regulator-min-microvolt = <1800000>; 247 regulator-max-microvolt = <3300000>; 248 status = "disabled"; 249 }; 250 }; 251 252 sdhi2: mmc@15c20000 { 253 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 254 reg = <0x0 0x15c20000 0 0x10000>; 255 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 258 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 259 clock-names = "core", "clkh", "cd", "aclk"; 260 resets = <&cpg 0xa9>; 261 power-domains = <&cpg>; 262 status = "disabled"; 263 264 sdhi2_vqmmc: vqmmc-regulator { 265 regulator-name = "SDHI2-VQMMC"; 266 regulator-min-microvolt = <1800000>; 267 regulator-max-microvolt = <3300000>; 268 status = "disabled"; 269 }; 270 }; 271 }; 272 273 timer { 274 compatible = "arm,armv8-timer"; 275 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 276 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 277 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 278 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 279 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 280 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 281 }; 282}; 283