1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org> 4 * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com> 5 */ 6 7#include <dt-bindings/clock/sophgo,cv1800.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/ { 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 osc: oscillator { 16 compatible = "fixed-clock"; 17 clock-output-names = "osc_25m"; 18 #clock-cells = <0>; 19 }; 20 21 soc { 22 compatible = "simple-bus"; 23 #address-cells = <1>; 24 #size-cells = <1>; 25 ranges; 26 27 gpio0: gpio@3020000 { 28 compatible = "snps,dw-apb-gpio"; 29 reg = <0x3020000 0x1000>; 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 porta: gpio-controller@0 { 34 compatible = "snps,dw-apb-gpio-port"; 35 gpio-controller; 36 #gpio-cells = <2>; 37 ngpios = <32>; 38 reg = <0>; 39 interrupt-controller; 40 #interrupt-cells = <2>; 41 interrupts = <SOC_PERIPHERAL_IRQ(44) IRQ_TYPE_LEVEL_HIGH>; 42 }; 43 }; 44 45 gpio1: gpio@3021000 { 46 compatible = "snps,dw-apb-gpio"; 47 reg = <0x3021000 0x1000>; 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 portb: gpio-controller@0 { 52 compatible = "snps,dw-apb-gpio-port"; 53 gpio-controller; 54 #gpio-cells = <2>; 55 ngpios = <32>; 56 reg = <0>; 57 interrupt-controller; 58 #interrupt-cells = <2>; 59 interrupts = <SOC_PERIPHERAL_IRQ(45) IRQ_TYPE_LEVEL_HIGH>; 60 }; 61 }; 62 63 gpio2: gpio@3022000 { 64 compatible = "snps,dw-apb-gpio"; 65 reg = <0x3022000 0x1000>; 66 #address-cells = <1>; 67 #size-cells = <0>; 68 69 portc: gpio-controller@0 { 70 compatible = "snps,dw-apb-gpio-port"; 71 gpio-controller; 72 #gpio-cells = <2>; 73 ngpios = <32>; 74 reg = <0>; 75 interrupt-controller; 76 #interrupt-cells = <2>; 77 interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_LEVEL_HIGH>; 78 }; 79 }; 80 81 gpio3: gpio@3023000 { 82 compatible = "snps,dw-apb-gpio"; 83 reg = <0x3023000 0x1000>; 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 portd: gpio-controller@0 { 88 compatible = "snps,dw-apb-gpio-port"; 89 gpio-controller; 90 #gpio-cells = <2>; 91 ngpios = <32>; 92 reg = <0>; 93 interrupt-controller; 94 #interrupt-cells = <2>; 95 interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_LEVEL_HIGH>; 96 }; 97 }; 98 99 saradc: adc@30f0000 { 100 compatible = "sophgo,cv1800b-saradc"; 101 reg = <0x030f0000 0x1000>; 102 clocks = <&clk CLK_SARADC>; 103 interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>; 104 #address-cells = <1>; 105 #size-cells = <0>; 106 status = "disabled"; 107 108 channel@0 { 109 reg = <0>; 110 }; 111 112 channel@1 { 113 reg = <1>; 114 }; 115 116 channel@2 { 117 reg = <2>; 118 }; 119 }; 120 121 i2c0: i2c@4000000 { 122 compatible = "snps,designware-i2c"; 123 reg = <0x04000000 0x10000>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>; 127 clock-names = "ref", "pclk"; 128 interrupts = <SOC_PERIPHERAL_IRQ(33) IRQ_TYPE_LEVEL_HIGH>; 129 status = "disabled"; 130 }; 131 132 i2c1: i2c@4010000 { 133 compatible = "snps,designware-i2c"; 134 reg = <0x04010000 0x10000>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>; 138 clock-names = "ref", "pclk"; 139 interrupts = <SOC_PERIPHERAL_IRQ(34) IRQ_TYPE_LEVEL_HIGH>; 140 status = "disabled"; 141 }; 142 143 i2c2: i2c@4020000 { 144 compatible = "snps,designware-i2c"; 145 reg = <0x04020000 0x10000>; 146 #address-cells = <1>; 147 #size-cells = <0>; 148 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>; 149 clock-names = "ref", "pclk"; 150 interrupts = <SOC_PERIPHERAL_IRQ(35) IRQ_TYPE_LEVEL_HIGH>; 151 status = "disabled"; 152 }; 153 154 i2c3: i2c@4030000 { 155 compatible = "snps,designware-i2c"; 156 reg = <0x04030000 0x10000>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>; 160 clock-names = "ref", "pclk"; 161 interrupts = <SOC_PERIPHERAL_IRQ(36) IRQ_TYPE_LEVEL_HIGH>; 162 status = "disabled"; 163 }; 164 165 i2c4: i2c@4040000 { 166 compatible = "snps,designware-i2c"; 167 reg = <0x04040000 0x10000>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>; 171 clock-names = "ref", "pclk"; 172 interrupts = <SOC_PERIPHERAL_IRQ(37) IRQ_TYPE_LEVEL_HIGH>; 173 status = "disabled"; 174 }; 175 176 uart0: serial@4140000 { 177 compatible = "snps,dw-apb-uart"; 178 reg = <0x04140000 0x100>; 179 interrupts = <SOC_PERIPHERAL_IRQ(28) IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>; 181 clock-names = "baudclk", "apb_pclk"; 182 reg-shift = <2>; 183 reg-io-width = <4>; 184 status = "disabled"; 185 }; 186 187 uart1: serial@4150000 { 188 compatible = "snps,dw-apb-uart"; 189 reg = <0x04150000 0x100>; 190 interrupts = <SOC_PERIPHERAL_IRQ(29) IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>; 192 clock-names = "baudclk", "apb_pclk"; 193 reg-shift = <2>; 194 reg-io-width = <4>; 195 status = "disabled"; 196 }; 197 198 uart2: serial@4160000 { 199 compatible = "snps,dw-apb-uart"; 200 reg = <0x04160000 0x100>; 201 interrupts = <SOC_PERIPHERAL_IRQ(30) IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>; 203 clock-names = "baudclk", "apb_pclk"; 204 reg-shift = <2>; 205 reg-io-width = <4>; 206 status = "disabled"; 207 }; 208 209 uart3: serial@4170000 { 210 compatible = "snps,dw-apb-uart"; 211 reg = <0x04170000 0x100>; 212 interrupts = <SOC_PERIPHERAL_IRQ(31) IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>; 214 clock-names = "baudclk", "apb_pclk"; 215 reg-shift = <2>; 216 reg-io-width = <4>; 217 status = "disabled"; 218 }; 219 220 spi0: spi@4180000 { 221 compatible = "snps,dw-apb-ssi"; 222 reg = <0x04180000 0x10000>; 223 #address-cells = <1>; 224 #size-cells = <0>; 225 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>; 226 clock-names = "ssi_clk", "pclk"; 227 interrupts = <SOC_PERIPHERAL_IRQ(38) IRQ_TYPE_LEVEL_HIGH>; 228 status = "disabled"; 229 }; 230 231 spi1: spi@4190000 { 232 compatible = "snps,dw-apb-ssi"; 233 reg = <0x04190000 0x10000>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>; 237 clock-names = "ssi_clk", "pclk"; 238 interrupts = <SOC_PERIPHERAL_IRQ(39) IRQ_TYPE_LEVEL_HIGH>; 239 status = "disabled"; 240 }; 241 242 spi2: spi@41a0000 { 243 compatible = "snps,dw-apb-ssi"; 244 reg = <0x041a0000 0x10000>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>; 248 clock-names = "ssi_clk", "pclk"; 249 interrupts = <SOC_PERIPHERAL_IRQ(40) IRQ_TYPE_LEVEL_HIGH>; 250 status = "disabled"; 251 }; 252 253 spi3: spi@41b0000 { 254 compatible = "snps,dw-apb-ssi"; 255 reg = <0x041b0000 0x10000>; 256 #address-cells = <1>; 257 #size-cells = <0>; 258 clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>; 259 clock-names = "ssi_clk", "pclk"; 260 interrupts = <SOC_PERIPHERAL_IRQ(41) IRQ_TYPE_LEVEL_HIGH>; 261 status = "disabled"; 262 }; 263 264 uart4: serial@41c0000 { 265 compatible = "snps,dw-apb-uart"; 266 reg = <0x041c0000 0x100>; 267 interrupts = <SOC_PERIPHERAL_IRQ(32) IRQ_TYPE_LEVEL_HIGH>; 268 clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>; 269 clock-names = "baudclk", "apb_pclk"; 270 reg-shift = <2>; 271 reg-io-width = <4>; 272 status = "disabled"; 273 }; 274 275 sdhci0: mmc@4310000 { 276 compatible = "sophgo,cv1800b-dwcmshc"; 277 reg = <0x4310000 0x1000>; 278 interrupts = <SOC_PERIPHERAL_IRQ(20) IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&clk CLK_AXI4_SD0>, 280 <&clk CLK_SD0>; 281 clock-names = "core", "bus"; 282 status = "disabled"; 283 }; 284 285 sdhci1: mmc@4320000 { 286 compatible = "sophgo,cv1800b-dwcmshc"; 287 reg = <0x4320000 0x1000>; 288 interrupts = <SOC_PERIPHERAL_IRQ(22) IRQ_TYPE_LEVEL_HIGH>; 289 clocks = <&clk CLK_AXI4_SD1>, 290 <&clk CLK_SD1>; 291 clock-names = "core", "bus"; 292 status = "disabled"; 293 }; 294 295 dmac: dma-controller@4330000 { 296 compatible = "snps,axi-dma-1.01a"; 297 reg = <0x04330000 0x1000>; 298 interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>; 300 clock-names = "core-clk", "cfgr-clk"; 301 #dma-cells = <1>; 302 dma-channels = <8>; 303 snps,block-size = <1024 1024 1024 1024 304 1024 1024 1024 1024>; 305 snps,priority = <0 1 2 3 4 5 6 7>; 306 snps,dma-masters = <2>; 307 snps,data-width = <2>; 308 status = "disabled"; 309 }; 310 }; 311}; 312