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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleA8.td1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
27 // Two fully-pipelined integer ALU pipelines
154 [1, 1, 1, 1, 3], [], -1>, // dynamic uops
159 [2, 1, 1, 1, 3], [], -1>, // dynamic uops
165 [1, 2, 1, 1, 3], [], -1>, // dynamic uops
170 [1, 1, 3], [], -1>, // dynamic uops
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H A DARMScheduleA9.td1 //=- ARMScheduleA9.td - ARM Cortex-A9 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.
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/freebsd/contrib/gdtoa/
H A DREADME1 This directory contains source for a library of binary -> decimal
2 and decimal -> binary conversion routines, for single-, double-,
3 and extended-precision IEEE binary floating-point arithmetic, and
4 other IEEE-like binary floating-point, including "double double",
7 T. J. Dekker, "A Floating-Point Technique for Extending the
8 Available Precision", Numer. Math. 18 (1971), pp. 224-242
12 "Inside Macintosh: PowerPC Numerics", Addison-Wesley, 1994
14 The conversion routines use double-precision floating-point arithmetic
15 and, where necessary, high precision integer arithmetic. The routines
18 David M. Gay, "Correctly Rounded Binary-Decimal and
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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/
H A Daddtf3.c1 //===-- lib/addtf3.c - Quad-precision addition --------------------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements quad-precision soft-float addition.
11 //===----------------------------------------------------------------------===//
H A Dmultf3.c1 //===-- lib/multf3.c - Quad-precision multiplication --------------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements quad-precision soft-float multiplication
10 // with the IEEE-754 default rounding (to nearest, ties to even).
12 //===----------------------------------------------------------------------===//
H A Ddivtf3.c1 //===-- lib/divtf3.c - Quad-precision division --------------------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements quad-precision soft-float division
10 // with the IEEE-754 default rounding (to nearest, ties to even).
12 //===----------------------------------------------------------------------===//
H A Dsubtf3.c1 //===-- lib/subtf3.c - Quad-precision subtraction -----------------*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements quad-precision soft-float subtraction.
11 //===----------------------------------------------------------------------===//
H A Dfloatunsitf.c1 //===-- lib/floatunsitf.c - uint -> quad-precision conversion -----*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements unsigned integer to quad-precision conversion for the
10 // compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
13 //===----------------------------------------------------------------------===//
28 const int exponent = (aWidth - 1) - clzsi(a); in __floatunsitf()
32 const int shift = significandBits - exponent; in __floatunsitf()
H A Dfloatunditf.c1 //===-- lib/floatunditf.c - uint -> quad-precision conversion -----*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements du_int to quad-precision conversion for the
10 // compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
13 //===----------------------------------------------------------------------===//
28 const int exponent = (aWidth - 1) - __builtin_clzll(a); in __floatunditf()
32 const int shift = significandBits - exponent; in __floatunditf()
H A Dfloatditf.c1 //===-- lib/floatditf.c - integer -> quad-precision conversion ----*- C -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file implements di_int to quad-precision conversion for the
10 // compiler-rt library in the IEEE-754 default round-to-nearest, ties-to-even
13 //===----------------------------------------------------------------------===//
36 const int exponent = (aWidth - 1) - __builtin_clzll(aAbs); in __floatditf()
39 // Shift a into the significand field, rounding if it is a right-shift in __floatditf()
40 const int shift = significandBits - exponent; in __floatditf()
H A Dfp_extend.h1 //===-lib/fp_extend.h - low precision -> high precision conversion -*- C
2 //-*-===//
6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
25 // -1 accounts for the sign bit.
26 // srcBits - srcSigFracBits - 1
36 // -1 accounts for the sign bit.
37 // srcBits - srcSigFracBits - 1
50 // -1 accounts for the sign bit.
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/freebsd/share/man/man7/
H A Darch.71 .\" Copyright (c) 2016-2017 The FreeBSD Foundation.
32 .Nd Architecture-specific details
40 For full details consult the processor-specific ABI supplement
97 .Bl -column -offset indent "Architecture" "Initial Release"
110 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
141 .Bl -tag -width "Dv L64PC128"
148 types machine representations all have 4-byte size.
172 Typically these are 64-bit machines, where the
178 environment, which was the historical 32-bit predecessor for 64-bit evolution.
180 .Bl -column -offset indent "powerpc64" "ILP32 counterpart"
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/freebsd/lib/msun/man/
H A Dieee.333 .Nd IEEE standard 754 for floating-point arithmetic
35 The IEEE Standard 754 for Binary Floating-Point Arithmetic
36 defines representations of floating-point numbers and abstract
37 properties of arithmetic operations relating to precision,
39 .Ss IEEE STANDARD 754 Floating-Point Arithmetic
43 .Bd -ragged -offset indent -compact
49 Zero is represented ambiguously as +0 or \-0.
50 .Bd -ragged -offset indent -compact
53 with like signs; but x\-x yields +0 for every
57 .Fn copysign x \(+-0 .
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/freebsd/lib/libc/quad/
H A Dmuldi3.c1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
8 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
36 #include "quad.h"
41 * Our algorithm is based on the following. Split incoming quad values
60 * (2^n) (u1 v0 - u1 v1 + u0 v1 - u0 v0) +
66 * (2^n) (u1 - u0) (v0 - v1) + [(u1-u0)... = mid]
69 * The terms (u1 v1), (u1 - u0) (v0 - v1), and (u0 v0) can all be done
70 * in just half the precision of the original. (Note that either or both
71 * of (u1 - u0) or (v0 - v1) may be negative.)
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/freebsd/sys/libkern/arm/
H A Dmuldi3.c3 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
38 #include <libkern/quad.h>
43 * Our algorithm is based on the following. Split incoming quad values
62 * (2^n) (u1 v0 - u1 v1 + u0 v1 - u0 v0) +
68 * (2^n) (u1 - u0) (v0 - v1) + [(u1-u0)... = mid]
71 * The terms (u1 v1), (u1 - u0) (v0 - v1), and (u0 v0) can all be done
72 * in just half the precision of the original. (Note that either or both
73 * of (u1 - u0) or (v0 - v1) may be negative.)
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/freebsd/contrib/file/doc/
H A Dmagic.man37 .Bl -tag -width ".Dv message"
42 .Bl -bullet -compact
50 A continuation offset relative to the end of the last up-level field
60 .Bl -tag -width ".Dv lestring16"
62 A one-byte value.
64 A two-byte value in this machine's native byte order.
66 A four-byte value in this machine's native byte order.
67 .It Dv quad
68 An eight-byte value in this machine's native byte order.
70 A 32-bit single precision IEEE floating point number in this machine's native byte order.
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/freebsd/contrib/arm-optimized-routines/math/aarch64/sve/
H A Dsinf.c2 * Single-precision SVE sin(x) function.
4 * Copyright (c) 2019-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
15 /* Pi-related values to be loaded as one quad-word and used with
21 /* Non-zero coefficients from the degree 9 Taylor series expansion of
23 -0x1.555548p-3f, 0x1.110df4p-7f, -0x1.9f42eap-13f, 0x1.5b2e76p-19f
25 .negpi1 = -0x1.921fb6p+1f,
26 .negpi2 = 0x1.777a5cp-24f,
27 .negpi3 = 0x1.ee59dap-49f,
28 .invpi = 0x1.45f306p-2f,
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H A Dexpm1.c2 * Double-precision vector exp(x) - 1 function.
4 * Copyright (c) 2023-2024, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
20 /* To be loaded in one quad-word. */
24 .poly = { 0x1p-1, 0x1.5555555555559p-3, 0x1.555555555554bp-5,
25 0x1.111111110f663p-7, 0x1.6c16c16c1b5f3p-10, 0x1.a01a01affa35dp-13,
26 0x1.a01a018b4ecbbp-16, 0x1.71ddf82db5bb4p-19, 0x1.27e517fc0d54bp-22,
27 0x1.af5eedae67435p-26, 0x1.1f143d060a28ap-29, },
31 .ln2_hi = 0x1.62e42fefa39efp-1,
32 .ln2_lo = 0x1.abc9e3b39803fp-56,
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/freebsd/contrib/file/src/
H A Dfmtcheck.c3 /*-
68 int sh, lg, quad, longdouble; in get_next_format_from_precision() local
71 sh = lg = quad = longdouble = 0; in get_next_format_from_precision()
84 quad = 1; in get_next_format_from_precision()
91 quad = 1; in get_next_format_from_precision()
105 quad = 1; in get_next_format_from_precision()
109 quad = 1; in get_next_format_from_precision()
123 if (quad) in get_next_format_from_precision()
134 if (quad) in get_next_format_from_precision()
139 if (sh + lg + quad + longdouble) in get_next_format_from_precision()
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/freebsd/lib/libc/aarch64/
H A DMakefile.inc2 # Machine dependent definitions for the arm 64-bit architecture.
5 # Long double is quad precision
/freebsd/lib/libc/riscv/
H A DMakefile.inc2 # Machine dependent definitions for the RISC-V architecture.
5 # Long double is quad precision
/freebsd/contrib/file/magic/Magdir/
H A Dpdp2 #------------------------------------------------------------------------------
4 # pdp: file(1) magic for PDP-11 executable/object and APL workspace
5 # URL: https://en.wikipedia.org/wiki/PDP-11
7 0 lelong 0101555 PDP-11 single precision APL workspace
8 0 lelong 0101554 PDP-11 double precision APL workspace
10 # PDP-11 a.out
12 0 leshort 0407 PDP-11 executable
14 >15 byte >0 - version %d
19 # PDP-11 UNIX/RT ldp (strength=50=50+0) after D64 Image (strength=70=70+0 ./c64) and MMDF mailbox (…
24 #>>15 byte !0 PDP-11 UNIX/RT ldp
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/freebsd/lib/msun/src/
H A Dk_rem_pio2.c18 * y = x - N*pi/2
27 * (2/pi) is represented by an array of 24-bit integers in ipio2[].
31 * pieces of 24-bit integers in double precision format.
32 * x[i] will be the i-th 24 bit of x. The scaled exponent
37 * e0 = ilogb(z)-23
38 * z = scalbn(z,-e0)
41 * z = (z-x[i])*2**24
44 * y[] output result in an array of double precision numbers.
46 * 24-bit precision 1
47 * 53-bit precision 2
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/freebsd/contrib/llvm-project/compiler-rt/
H A DCREDITS.TXT7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), and snail-mail address
19 D: CMake'ify Compiler-RT build system
20 D: Maintain Solaris & AuroraUX ports of Compiler-RT
24 D: Architect and primary author of compiler-rt
26 N: Guan-Hong Liu
28 D: IEEE Quad-precision functions
/freebsd/lib/libc/gdtoa/
H A Dmachdep_ldisQ.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
35 * Machine-dependent glue to integrate David Gay's gdtoa
37 * uses quad precision, such as aarch64 or riscv.

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