Lines Matching +full:quad +full:- +full:precision
1 //=- ARMScheduleA8.td - ARM Cortex-A8 Scheduling Definitions -*- tablegen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 // Scheduling information derived from "Cortex-A8 Technical Reference Manual".
27 // Two fully-pipelined integer ALU pipelines
154 [1, 1, 1, 1, 3], [], -1>, // dynamic uops
159 [2, 1, 1, 1, 3], [], -1>, // dynamic uops
165 [1, 2, 1, 1, 3], [], -1>, // dynamic uops
170 [1, 1, 3], [], -1>, // dynamic uops
176 [1, 1, 3], [], -1>, // dynamic uops
232 [], [], -1>, // dynamic uops
237 [2], [], -1>, // dynamic uops
249 // RunFast mode so that NFP pipeline is used for single-precision when
256 // Single-precision FP Unary
260 // Double-precision FP Unary
265 // Single-precision FP Compare
269 // Double-precision FP Compare
284 // Single-Precision FP to Integer Convert
288 // Double-Precision FP to Integer Convert
293 // Integer to Single-Precision FP Convert
297 // Integer to Double-Precision FP Convert
302 // Single-precision FP ALU
306 // Double-precision FP ALU
311 // Single-precision FP Multiply
315 // Double-precision FP Multiply
320 // Single-precision FP MAC
324 // Double-precision FP MAC
329 // Single-precision Fused FP MAC
333 // Double-precision Fused FP MAC
338 // Single-precision FP DIV
343 // Double-precision FP DIV
348 // Single-precision FP SQRT
353 // Double-precision FP SQRT
359 // Integer to Single-precision Move
364 // Integer to Double-precision Move
369 // Single-precision to Integer Move
374 // Double-precision to Integer Move
380 // Single-precision FP Load
386 // Double-precision FP Load
399 [1, 1, 1, 2], [], -1>, // dynamic uops
407 [2, 1, 1, 1, 2], [], -1>, // dynamic uops
409 // Single-precision FP Store
415 // Double-precision FP Store
427 [1, 1, 1, 1], [], -1>, // dynamic uops
435 [2, 1, 1, 1, 1], [], -1>, // dynamic uops
774 // Double-register FP Unary
778 // Quad-register FP Unary
784 // Double-register FP Binary
792 // Double-register FP VMUL
797 // Quad-register FP Binary
803 // Quad-register FP VMUL
815 // Double-register Permute Move
819 // Quad-register Permute Move
825 // Integer to Single-precision Move
829 // Integer to Double-precision Move
833 // Single-precision to Integer Move
837 // Double-precision to Integer Move
849 // Double-register Permute
853 // Quad-register Permute
859 // Quad-register Permute (3 cycle issue)
867 // Double-register FP Multiple-Accumulate
871 // Quad-register FP Multiple-Accumulate
877 // Double-register Fused FP Multiple-Accumulate
881 // Quad-register Fused FP Multiple-Accumulate
887 // Double-register Reciprical Step
891 // Quad-register Reciprical Step
895 // Double-register Integer Count
899 // Quad-register Integer Count
905 // Double-register Integer Unary
909 // Quad-register Integer Unary
913 // Double-register Integer Q-Unary
917 // Quad-register Integer CountQ-Unary
921 // Double-register Integer Binary
925 // Quad-register Integer Binary
929 // Double-register Integer Binary (4 cycle)
933 // Quad-register Integer Binary (4 cycle)
938 // Double-register Integer Subtract
942 // Quad-register Integer Subtract
946 // Double-register Integer Subtract
950 // Quad-register Integer Subtract
954 // Double-register Integer Shift
958 // Quad-register Integer Shift
962 // Double-register Integer Shift (4 cycle)
966 // Quad-register Integer Shift (4 cycle)
970 // Double-register Integer Pair Add Long
974 // Quad-register Integer Pair Add Long
978 // Double-register Absolute Difference and Accumulate
982 // Quad-register Absolute Difference and Accumulate
987 // Double-register Integer Multiply (.8, .16)
991 // Double-register Integer Multiply (.32)
995 // Quad-register Integer Multiply (.8, .16)
999 // Quad-register Integer Multiply (.32)
1005 // Double-register Integer Multiply-Accumulate (.8, .16)
1009 // Double-register Integer Multiply-Accumulate (.32)
1013 // Quad-register Integer Multiply-Accumulate (.8, .16)
1017 // Quad-register Integer Multiply-Accumulate (.32)
1023 // Double-register VEXT
1027 // Quad-register VEXT
1060 // ===---------------------------------------------------------------------===//
1064 // Cortex-A8 machine model for scheduling and other instruction cost heuristics.
1066 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.