Lines Matching +full:quad +full:- +full:precision
1 .\" Copyright (c) 2016-2017 The FreeBSD Foundation.
32 .Nd Architecture-specific details
40 For full details consult the processor-specific ABI supplement
97 .Bl -column -offset indent "Architecture" "Initial Release"
110 .Bl -column -offset indent "Architecture" "Initial Release" "Final Release"
141 .Bl -tag -width "Dv L64PC128"
148 types machine representations all have 4-byte size.
172 Typically these are 64-bit machines, where the
178 environment, which was the historical 32-bit predecessor for 64-bit evolution.
180 .Bl -column -offset indent "powerpc64" "ILP32 counterpart"
198 Architectures with 128-bit capabilities support both a
204 .Bl -column -offset indent "aarch64c" "LP64 counterpart"
211 .Bl -column -offset indent "long long" "Size"
225 requires only 4-byte alignment for 64-bit integers.
227 Machine-dependent type sizes:
228 .Bl -column -offset indent "Architecture" "long" "void *" "long double" "time_t"
246 .Bl -column -offset indent "Architecture" "Endianness" "char Signedness"
261 .Bl -column -offset indent "Architecture" "Page Sizes"
276 .Bl -column -offset indent "riscv64 (Sv48)" "0x0001000000000000" "NNNU"
299 Historically, amd64 CPUs were limited to a 48-bit virtual address space.
300 Newer CPUs support 5-level page tables, which extend the significant bits of
305 tunable to 0 forces the system into 4-level paging mode, even on hardware that
306 supports 5-level paging.
307 In this mode, all processes get a 48-bit address space.
311 a 48-bit address space by default.
322 The RISC-V specification permits 3-level (Sv39), 4-level (Sv48), and
323 5-level (Sv57) page tables.
333 .Bl -column -offset indent "Architecture" "float, double" "long double"
335 .It aarch64 Ta hard Ta soft, quad precision
336 .It aarch64c Ta hard Ta soft, quad precision
338 .It armv7 Ta hard Ta hard, double precision
340 .It powerpc Ta hard Ta hard, double precision
341 .It powerpcspe Ta hard Ta hard, double precision
342 .It powerpc64 Ta hard Ta hard, double precision
343 .It powerpc64le Ta hard Ta hard, double precision
344 .It riscv64 Ta hard Ta hard, quad precision
345 .It riscv64c Ta hard Ta hard, quad precision
370 .Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
381 Some of these provide architecture-specific details and are explained below.
386 .Bd -literal -offset indent
387 cc -x c -dM -E /dev/null
391 .Bl -column -offset indent "__SIZEOF_POINTER__" "Meaning"
396 .It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
397 .It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
398 .It Dv __CHERI__ Ta 128-bit (16-byte) capability pointer, 64-bit (8-byte) long
418 as their pointers are 128-bit capabilities.
420 Architecture-specific macros:
421 .Bl -column -offset indent "Architecture" "Predefined macros"
436 Compilers may define additional variants of architecture-specific macros.
445 .Bl -tag -width "MACHINE_CPUARCH"
469 of i386 supported the IBM-AT hardware platform while the
471 of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
489 It may also encode a variation in the byte ordering of multi-byte
503 If we ever were to support the so-called x32 ABI (using 32-bit
505 as amd64-x32.
506 It is unfortunate that amd64 specifies the 64-bit evolution of the x86 platform