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/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dfsl,qe-muram.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-muram.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine Multi-User RAM (MURAM)
10 - Frank Li <Frank.Li@nxp.com>
12 description: Multi-User RAM (MURAM)
17 - const: fsl,qe-muram
18 - const: fsl,cpm-muram
23 "#address-cells":
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H A Dfsl,qe.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QUICC Engine module (QE)
10 - Frank Li <Frank.Li@nxp.com>
13 This represents qe module that is installed on PowerQUICC II Pro.
20 the "root" qe node, using the common properties from there.
21 The description below applies to the qe of MPC8360 and
27 - const: fsl,qe
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H A Dcpm.txt4 as more devices are supported. The QE bindings especially are
10 - compatible : "fsl,cpm1", "fsl,cpm2", or "fsl,qe".
11 - reg : A 48-byte region beginning with CPCR.
15 #address-cells = <1>;
16 #size-cells = <1>;
17 #interrupt-cells = <2>;
18 compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
22 * Properties common to multiple CPM/QE devices
24 - fsl,cpm-command : This value is ORed with the opcode and command flag
27 - fsl,cpm-brg : Indicates which baud rate generator the device
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/linux/arch/powerpc/boot/dts/fsl/
H A Dt1024si-post.dtsi29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
35 #include "t1023si-post.dtsi"
43 qe:qe@ffe140000 { label
44 #address-cells = <1>;
45 #size-cells = <1>;
46 device_type = "qe";
47 compatible = "fsl,qe";
50 fsl,qe-num-riscs = <1>;
51 fsl,qe-num-snums = <28>;
52 brg-frequency = <0>;
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H A Dmpc8569si-post.dtsi29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8569-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
56 #interrupt-cells = <1>;
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H A Dp1021si-post.dtsi4 * Copyright 2011-2012 Freescale Semiconductor Inc.
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,p1021-elbc", "fsl,elbc", "simple-bus";
45 compatible = "fsl,mpc8548-pcie";
47 #size-cells = <2>;
48 #address-cells = <3>;
49 bus-range = <0 255>;
50 clock-frequency = <33333333>;
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H A Dmpc8568si-post.dtsi29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,mpc8568-localbus", "fsl,pq3-localbus", "simple-bus";
45 compatible = "fsl,mpc8540-pci";
48 bus-range = <0 0xff>;
49 #interrupt-cells = <1>;
50 #size-cells = <2>;
51 #address-cells = <3>;
57 compatible = "fsl,mpc8548-pcie";
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H A Dt1040si-post.dtsi4 * Copyright 2013 - 2014 Freescale Semiconductor Inc.
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
35 #include <dt-bindings/thermal/thermal.h>
38 compatible = "fsl,bman-fbpr";
39 alloc-ranges = <0 0 0x10000 0>;
43 compatible = "fsl,qman-fqd";
44 alloc-ranges = <0 0 0x10000 0>;
48 compatible = "fsl,qman-pfdr";
49 alloc-ranges = <0 0 0x10000 0>;
53 #address-cells = <2>;
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/linux/drivers/soc/fsl/qe/
H A Dqe_common.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
11 * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
26 #include <soc/fsl/qe/qe.h>
57 np = of_find_compatible_node(NULL, NULL, "fsl,cpm-muram-data"); in cpm_muram_init()
60 np = of_find_node_by_name(NULL, "data-only"); in cpm_muram_init()
62 pr_err("Cannot find CPM muram data node"); in cpm_muram_init()
63 ret = -ENODEV; in cpm_muram_init()
68 muram_pool = gen_pool_create(0, -1); in cpm_muram_init()
70 pr_err("Cannot allocate memory pool for CPM/QE muram"); in cpm_muram_init()
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H A Ducc_slow.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * QE UCC Slow API Set - UCC Slow specific routines implementations.
20 #include <soc/fsl/qe/immap_qe.h>
21 #include <soc/fsl/qe/qe.h>
23 #include <soc/fsl/qe/ucc.h>
24 #include <soc/fsl/qe/ucc_slow.h>
44 struct ucc_slow_info *us_info = uccs->us_info; in ucc_slow_graceful_stop_tx()
47 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_graceful_stop_tx()
55 struct ucc_slow_info *us_info = uccs->us_info; in ucc_slow_stop_tx()
58 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num); in ucc_slow_stop_tx()
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H A Ducc_fast.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 * QE UCC Fast API Set - UCC Fast specific routines implementations.
20 #include <soc/fsl/qe/immap_qe.h>
21 #include <soc/fsl/qe/qe.h>
23 #include <soc/fsl/qe/ucc.h>
24 #include <soc/fsl/qe/ucc_fast.h>
28 printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num); in ucc_fast_dump_regs()
29 printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs); in ucc_fast_dump_regs()
32 &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr)); in ucc_fast_dump_regs()
34 &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr)); in ucc_fast_dump_regs()
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H A Dqe.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
11 * QUICC Engine (QE).
30 #include <soc/fsl/qe/immap_qe.h>
31 #include <soc/fsl/qe/qe.h>
50 static phys_addr_t qebase = -1;
54 struct device_node *qe; in qe_get_device_node() local
57 * Newer device trees have an "fsl,qe" compatible property for the QE in qe_get_device_node()
60 qe = of_find_compatible_node(NULL, NULL, "fsl,qe"); in qe_get_device_node()
61 if (qe) in qe_get_device_node()
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/linux/arch/powerpc/boot/dts/
H A Dmpc836x_rdk.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2007-2008 MontaVista Software, Inc.
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
31 #address-cells = <1>;
32 #size-cells = <0>;
37 d-cache-line-size = <32>;
38 i-cache-line-size = <32>;
39 d-cache-size = <32768>;
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H A Dmpc832x_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <0x20>; // 32 bytes
32 i-cache-line-size = <0x20>; // 32 bytes
33 d-cache-size = <16384>; // L1, 16K
34 i-cache-size = <16384>; // L1, 16K
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H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
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/linux/include/soc/fsl/qe/
H A Ducc_slow.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #include <soc/fsl/qe/immap_qe.h>
17 #include <soc/fsl/qe/qe.h>
19 #include <soc/fsl/qe/ucc.h>
28 #define T_A 0x04000000 /* Address - the data transmitted as address
33 #define T_P 0x01000000 /* Preamble - send Preamble sequence before
34 data */
74 /* Rx Data buffer must be 4 bytes aligned in most cases.*/
89 /* 16-bit CCITT CRC (HDLC). (X16 + X12 + X5 + 1) */
93 /* 32-bit CCITT CRC (Ethernet and HDLC) */
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H A Dimmap_qe.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QUICC Engine (QE) Internal Memory Map.
4 * The Internal Memory Map for devices with QE on them. This
5 * is the superset of all QE devices (8360, etc.).
22 /* QE I-RAM */
24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
31 /* QE Interrupt Controller */
56 __be32 cecr; /* QE command register */
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
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