Lines Matching +full:qe +full:- +full:muram +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
11 * QUICC Engine (QE).
30 #include <soc/fsl/qe/immap_qe.h>
31 #include <soc/fsl/qe/qe.h>
50 static phys_addr_t qebase = -1;
54 struct device_node *qe;
57 * Newer device trees have an "fsl,qe" compatible property for the QE
60 qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
61 if (qe)
62 return qe;
63 return of_find_node_by_type(NULL, "qe");
68 struct device_node *qe;
72 if (qebase != -1)
75 qe = qe_get_device_node();
76 if (!qe)
79 ret = of_address_to_resource(qe, 0, &res);
82 of_node_put(qe);
97 /* Reclaim the MURAM memory for our use. */
113 iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
116 /* Here device is the SNUM, not sub-block */
130 iowrite32be(cmd_input, &qe_immr->cp.cecdr);
132 &qe_immr->cp.cecr);
136 ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val,
138 /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
146 * 16 BRGs, which can be connected to the QE channels or output
149 * The BRG clock is the QE clock divided by 2.
152 * Baud rate clocks are zero-based in the driver code (as that maps
153 * to port numbers). Documentation uses 1-based numbering.
162 struct device_node *qe;
169 qe = qe_get_device_node();
170 if (!qe)
173 if (!of_property_read_u32(qe, "brg-frequency", &brg))
176 of_node_put(qe);
182 brg_clk -= mod;
183 else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
184 brg_clk += CLK_GRAN - mod;
204 * @brg: the BRG, QE_BRG1 - QE_BRG16
216 return -EINVAL;
226 that the BRG divisor must be even if you're not using divide-by-16
232 tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
235 iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
241 /* Convert a string to a QE clock source enum
262 return (QE_BRG1 - 1) + i;
270 return (QE_CLK1 - 1) + i;
280 * QE Module Control chapter, SNUM table
304 struct device_node *qe;
310 qe = qe_get_device_node();
311 if (qe) {
312 i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
315 of_node_put(qe);
321 * fsl,qe-num-snums to choose one of the static arrays
324 of_property_read_u32(qe, "fsl,qe-num-snums", &qe_num_of_snum);
325 of_node_put(qe);
333 pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n", qe_num_of_snum);
342 int snum = -EBUSY;
362 clear_bit(p - snums, snum_state);
368 struct sdma __iomem *sdma = &qe_immr->sdma;
369 static s32 sdma_buf_offset = -ENOMEM;
376 return -ENOMEM;
380 &sdma->sdebcr);
382 &sdma->sdmr);
394 * Set to 1 if QE firmware has been uploaded, and therefore
395 * qe_firmware_info contains valid data.
400 * Upload a QE microcode
408 const __be32 *code = base + be32_to_cpu(ucode->code_offset);
411 if (ucode->major || ucode->minor || ucode->revision)
412 printk(KERN_INFO "qe-firmware: "
414 ucode->id, ucode->major, ucode->minor, ucode->revision);
416 printk(KERN_INFO "qe-firmware: "
417 "uploading microcode '%s'\n", ucode->id);
419 /* Use auto-increment */
420 iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
421 &qe_immr->iram.iadd);
423 for (i = 0; i < be32_to_cpu(ucode->count); i++)
424 iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
426 /* Set I-RAM Ready Register */
427 iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
431 * Upload a microcode to the I-RAM at a specific address.
433 * See Documentation/arch/powerpc/qe_firmware.rst for information on QE microcode
457 printk(KERN_ERR "qe-firmware: invalid pointer\n");
458 return -EINVAL;
461 hdr = &firmware->header;
462 length = be32_to_cpu(hdr->length);
465 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
466 (hdr->magic[2] != 'F')) {
467 printk(KERN_ERR "qe-firmware: not a microcode\n");
468 return -EPERM;
472 if (hdr->version != 1) {
473 printk(KERN_ERR "qe-firmware: unsupported version\n");
474 return -EPERM;
478 if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
479 printk(KERN_ERR "qe-firmware: invalid data\n");
480 return -EINVAL;
484 calc_size = struct_size(firmware, microcode, firmware->count);
486 for (i = 0; i < firmware->count; i++)
493 be32_to_cpu(firmware->microcode[i].count);
497 printk(KERN_ERR "qe-firmware: invalid length\n");
498 return -EPERM;
504 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
505 return -EIO;
509 * If the microcode calls for it, split the I-RAM.
511 if (!firmware->split)
512 qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
514 if (firmware->soc.model)
516 "qe-firmware: firmware '%s' for %u V%u.%u\n",
517 firmware->id, be16_to_cpu(firmware->soc.model),
518 firmware->soc.major, firmware->soc.minor);
520 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
521 firmware->id);
524 * The QE only supports one microcode per RISC, so clear out all the
528 strscpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
529 qe_firmware_info.extended_modes = be64_to_cpu(firmware->extended_modes);
530 memcpy(qe_firmware_info.vtraps, firmware->vtraps,
531 sizeof(firmware->vtraps));
534 for (i = 0; i < firmware->count; i++) {
535 const struct qe_microcode *ucode = &firmware->microcode[i];
538 if (ucode->code_offset)
543 u32 trap = be32_to_cpu(ucode->traps[j]);
547 &qe_immr->rsp[i].tibcr[j]);
551 iowrite32be(be32_to_cpu(ucode->eccr),
552 &qe_immr->rsp[i].eccr);
562 * Get info on the currently-loaded firmware
570 struct device_node *qe;
586 qe = qe_get_device_node();
587 if (!qe)
591 fw = of_get_child_by_name(qe, "firmware");
592 of_node_put(qe);
600 /* Copy the data into qe_firmware_info*/
606 of_property_read_u64(fw, "extended-modes",
609 of_property_read_u32_array(fw, "virtual-traps", qe_firmware_info.vtraps,
620 struct device_node *qe;
623 qe = qe_get_device_node();
624 if (!qe)
627 of_property_read_u32(qe, "fsl,qe-num-riscs", &num_of_risc);
629 of_node_put(qe);
645 np = of_find_compatible_node(NULL, NULL, "fsl,qe");
647 return -ENODEV;
668 { .compatible = "fsl,qe", },
674 .name = "fsl-qe",