Lines Matching +full:qe +full:- +full:muram +full:- +full:data
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * QUICC Engine (QE) Internal Memory Map.
4 * The Internal Memory Map for devices with QE on them. This
5 * is the superset of all QE devices (8360, etc.).
22 /* QE I-RAM */
24 __be32 iadd; /* I-RAM Address Register */
25 __be32 idata; /* I-RAM Data Register */
27 __be32 iready; /* I-RAM Ready Register */
31 /* QE Interrupt Controller */
56 __be32 cecr; /* QE command register */
57 __be32 ceccr; /* QE controller configuration register */
58 __be32 cecdr; /* QE command data register */
60 __be16 ceter; /* QE timer event register */
62 __be16 cetmr; /* QE timers mask register */
63 __be32 cetscr; /* QE time-stamp timer control register */
64 __be32 cetsr1; /* QE time-stamp register 1 */
65 __be32 cetsr2; /* QE time-stamp register 2 */
67 __be32 cevter; /* QE virtual tasks event register */
68 __be32 cevtmr; /* QE virtual tasks mask register */
69 __be16 cercr; /* QE RAM control register */
72 __be16 ceexe1; /* QE external request 1 event register */
74 __be16 ceexm1; /* QE external request 1 mask register */
76 __be16 ceexe2; /* QE external request 2 event register */
78 __be16 ceexm2; /* QE external request 2 mask register */
80 __be16 ceexe3; /* QE external request 3 event register */
82 __be16 ceexm3; /* QE external request 3 mask register */
84 __be16 ceexe4; /* QE external request 4 event register */
86 __be16 ceexm4; /* QE external request 4 mask register */
88 __be32 ceurnr; /* QE microcode revision number register */
92 /* QE Multiplexer */
103 /* QE Timers */
152 __be32 spitd; /* SPI transmit data register (cpu mode) */
153 __be32 spird; /* SPI receive data register (cpu mode) */
236 /* QE UCC Slow */
240 __be16 upsmr; /* UCCx protocol-specific mode register */
243 __be16 udsr; /* UCCx data synchronization register */
255 /* QE UCC Fast */
258 __be32 upsmr; /* UCCx protocol-specific mode register */
261 __be16 udsr; /* UCCx data synchronization register */
390 * the QE Developer's Handbook.
420 u8 res4[0x100-0xf8];
424 struct qe_iram iram; /* I-RAM */
427 struct qe_mux qmx; /* QE Multiplexer */
428 struct qe_timers qet; /* QE Timers */
449 struct dbg dbg; /* 0x104080 - 0x1040FF
451 struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF
454 u8 res14[0x300]; /* 0x104300 - 0x1045FF */
455 u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */
456 u8 res16[0x8000]; /* 0x108000 - 0x110000 */
457 u8 muram[0xC000]; /* 0x110000 - 0x11C000 member
458 Multi-user RAM */
459 u8 res17[0x24000]; /* 0x11C000 - 0x140000 */
460 u8 res18[0xC0000]; /* 0x140000 - 0x200000 */