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/linux/drivers/pwm/
H A Dpwm-jz4740.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
7 * - The .apply callback doesn't complete the currently running period before
15 #include <linux/mfd/ingenic-tcu.h>
20 #include <linux/pwm.h>
28 struct regmap *map; member
39 /* Enable all TCU channels for PWM use by default except channels 0/1 */ in jz4740_pwm_can_use_chn()
40 u32 pwm_channels_mask = GENMASK(chip->npwm - 1, 2); in jz4740_pwm_can_use_chn()
42 device_property_read_u32(pwmchip_parent(chip)->parent, in jz4740_pwm_can_use_chn()
[all …]
H A Dpwm-rz-mtu3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RZ/G2L MTU3a PWM Timer driver
8 …* https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?lang…
11 * - When PWM is disabled, the output is driven to Hi-Z.
12 * - While the hardware supports both polarities, the driver (for now)
14 * - HW uses one counter and two match components to configure duty_cycle
16 * - Multi-Function Timer Pulse Unit (a.k.a MTU) has 7 HW channels for PWM
18 * - MTU{1, 2} channels have a single IO, whereas all other HW channels have
20 * - Each IO is modelled as an independent PWM channel.
21 * - rz_mtu3_channel_io_map table is used to map the PWM channel to the
[all …]
H A Dpwm-xilinx.c1 // SPDX-License-Identifier: GPL-2.0+
6 * - When changing both duty cycle and period, we may end up with one cycle
13 * - Cannot produce 100% duty cycle by configuring the TLRs. This might be
16 * - Only produces "normal" output.
17 * - Always produces low output if disabled.
20 #include <clocksource/timer-xilinx.h>
22 #include <linux/clk-provider.h>
27 #include <linux/pwm.h>
37 WARN_ON(cycles < 2 || cycles - 2 > priv->max); in xilinx_timer_tlr_cycles()
40 return cycles - 2; in xilinx_timer_tlr_cycles()
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H A Dpwm-lp3943.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI/National Semiconductor LP3943 PWM driver
15 #include <linux/pwm.h>
36 struct lp3943_platform_data *pdata = lp3943_pwm->pdata; in lp3943_pwm_request_map()
37 struct lp3943 *lp3943 = lp3943_pwm->lp3943; in lp3943_pwm_request_map()
38 struct lp3943_pwm_map *pwm_map = &lp3943_pwm->pwm_map[hwpwm]; in lp3943_pwm_request_map()
41 pwm_map->output = pdata->pwms[hwpwm]->output; in lp3943_pwm_request_map()
42 pwm_map->num_outputs = pdata->pwms[hwpwm]->num_outputs; in lp3943_pwm_request_map()
44 for (i = 0; i < pwm_map->num_outputs; i++) { in lp3943_pwm_request_map()
45 offset = pwm_map->output[i]; in lp3943_pwm_request_map()
[all …]
H A Dpwm-intel-lgm.c1 // SPDX-License-Identifier: GPL-2.0
6 * - The hardware supports fixed period & configures only 2-wire mode.
7 * - Supports normal polarity. Does not support changing polarity.
8 * - When PWM is disabled, output of PWM will become 0(inactive). It doesn't
10 * - When duty cycle is changed, PWM output may be a mix of previous setting
13 * - It is a dedicated PWM fan controller. There are no other consumers for
14 * this PWM controller.
21 #include <linux/pwm.h>
36 #define LGM_PWM_MAX_RPM (BIT(16) - 1)
38 #define LGM_PWM_MAX_DUTY_CYCLE (BIT(8) - 1)
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/linux/arch/loongarch/boot/dts/
H A Dloongson-2k2000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
34 ref_100m: clock-ref-100m {
35 compatible = "fixed-clock";
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H A Dloongson-2k1000.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
35 ref_100m: clock-ref-100m {
[all …]
H A Dloongson-2k0500.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/clock/loongson,ls2k-clk.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
16 #address-cells = <1>;
17 #size-cells = <0>;
27 ref_100m: clock-ref-100m {
28 compatible = "fixed-clock";
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/linux/Documentation/devicetree/bindings/pwm/
H A Dpwm.txt1 Specifying PWM information for devices
4 1) PWM user nodes
5 -----------------
7 PWM users should specify a list of PWM devices that they want to use
8 with a property containing a 'pwm-list':
10 pwm-list ::= <single-pwm> [pwm-list]
11 single-pwm ::= <pwm-phandle> <pwm-specifier>
12 pwm-phandle : phandle to PWM controller node
13 pwm-specifier : array of #pwm-cells specifying the given PWM
16 PWM properties should be named "pwms". The exact meaning of each pwms
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/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8226-samsung-matisse-common.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
7 * The .dts should first include qcom-msm8226.dtsi or msm8926.dtsi depending on
11 #include <dt-bindings/input/input.h>
14 /delete-node/ &adsp_region;
15 /delete-node/ &mba_region;
16 /delete-node/ &mpss_region;
17 /delete-node/ &smem_region;
27 #address-cells = <1>;
28 #size-cells = <1>;
31 stdout-path = "display0";
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H A Dqcom-apq8026-lg-lenok.dts1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include "qcom-msm8226.dtsi"
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
12 /delete-node/ &adsp_region;
17 chassis-type = "watch";
18 qcom,board-id = <132 0x0a>;
19 qcom,msm-id = <199 0x20000>;
27 stdout-path = "serial0:115200n8";
30 reserved-memory {
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/linux/Documentation/devicetree/bindings/mfd/
H A Dairoha,en7581-gpio-sysctl.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/airoha,en7581-gpio-sysctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christian Marangi <ansuelsmth@gmail.com>
11 - Lorenzo Bianconi <lorenzo@kernel.org>
14 Airoha EN7581 SoC GPIO system controller which provided a register map
15 for controlling the GPIO, pins and PWM of the SoC.
20 - const: airoha,en7581-gpio-sysctl
21 - const: syscon
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra194-clock.h>
3 #include <dt-bindings/gpio/tegra194-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
8 #include <dt-bindings/power/tegra194-powergate.h>
9 #include <dt-bindings/reset/tegra194-reset.h>
10 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
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/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78230.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
25 #address-cells = <1>;
26 #size-cells = <0>;
27 enable-method = "marvell,armada-xp-smp";
31 compatible = "marvell,sheeva-v7";
34 clock-latency = <1000000>;
39 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78260.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
26 #address-cells = <1>;
27 #size-cells = <0>;
28 enable-method = "marvell,armada-xp-smp";
32 compatible = "marvell,sheeva-v7";
35 clock-latency = <1000000>;
40 compatible = "marvell,sheeva-v7";
[all …]
H A Darmada-xp-mv78460.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include "armada-xp.dtsi"
17 compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
27 #address-cells = <1>;
28 #size-cells = <0>;
29 enable-method = "marvell,armada-xp-smp";
33 compatible = "marvell,sheeva-v7";
36 clock-latency = <1000000>;
41 compatible = "marvell,sheeva-v7";
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-th1520.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl driver for the T-Head TH1520 SoC
26 #include <linux/pinctrl/pinconf-generic.h>
67 return thp->base + 4 * (pin / 2); in th1520_padcfg()
78 return thp->base + 0x400 + 4 * (pin / 8); in th1520_muxcfg()
115 [TH1520_MUX_PWM] = "pwm",
284 TH1520_PAD(2, QSPI0_SCLK, QSPI, PWM, I2S, GPIO, ____, ____, 0),
285 TH1520_PAD(3, QSPI0_CSN0, QSPI, PWM, I2S, GPIO, ____, ____, 0),
286 TH1520_PAD(4, QSPI0_CSN1, QSPI, PWM, I2S, GPIO, ____, ____, 0),
287 TH1520_PAD(5, QSPI0_D0_MOSI, QSPI, PWM, I2S, GPIO, ____, ____, 0),
[all …]
/linux/drivers/hwmon/
H A Dgxp-fan-ctrl.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (C) 2022 Hewlett-Packard Enterprise Development Company, L.P. */
28 val = readb(drvdata->plreg + OFS_FAN_INST); in fan_installed()
38 val = readb(drvdata->plreg + OFS_FAN_FAIL); in fan_failed()
50 * reported for the PWM will be incorrect. Report fan as in fan_enabled()
53 val = readl(drvdata->fn2 + OFS_SEVSTAT); in fan_enabled()
65 return -EINVAL; in gxp_pwm_write()
66 writeb(val, drvdata->base + channel); in gxp_pwm_write()
69 return -EOPNOTSUPP; in gxp_pwm_write()
80 return -EOPNOTSUPP; in gxp_fan_ctrl_write()
[all …]
H A Dmlxreg-fan.c1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
27 * FAN datasheet defines the formula for RPM calculations as RPM = 15/t-high.
28 * The logic in a programmable device measures the time t-high by sampling the
29 * tachometer every t-sample (with the default value 11.32 uS) and increment
31 * RPM = 15 / (t-sample * (K + Regval)), where:
33 * - 0xff - represents tachometer fault;
34 * - 0xfe - represents tachometer minimum value , which is 4444 RPM;
35 * - 0x00 - represents tachometer maximum value , which is 300000 RPM;
39 * used: RPM = 15 / ((Regval + K) * 11.32) * 10^(-6)), which in the
42 * - for Regval 0x00, RPM will be 15000000 * 100 / (44 * 1132) = 30115;
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-g12b-odroid.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/gpio/meson-g12a-gpio.h>
9 #include <dt-bindings/sound/meson-g12a-toacodec.h>
10 #include <dt-bindings/sound/meson-g12a-tohdmitx.h>
20 stdout-path = "serial0:115200n8";
28 emmc_pwrseq: emmc-pwrseq {
29 compatible = "mmc-pwrseq-emmc";
30 reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
33 fan: gpio-fan {
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-linksys-nslu2.dts1 // SPDX-License-Identifier: ISC
6 /dts-v1/;
8 #include "intel-ixp42x.dtsi"
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
25 stdout-path = "uart0:115200n8";
33 compatible = "gpio-leds";
34 led-status {
37 default-state = "on";
[all …]
/linux/drivers/clocksource/
H A Dingenic-timer.c1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/mfd/ingenic-tcu.h>
23 #include <dt-bindings/clock/ingenic,tcu.h>
40 struct regmap *map; member
56 regmap_read(tcu->map, TCU_REG_TCNTc(tcu->cs_channel), &count); in ingenic_tcu_timer_read()
69 return container_of(timer, struct ingenic_tcu, timers[timer->cpu]); in to_ingenic_tcu()
83 regmap_write(tcu->map, TCU_REG_TECR, BIT(timer->channel)); in ingenic_tcu_cevt_set_state_shutdown()
95 return -EINVAL; in ingenic_tcu_cevt_set_next()
97 regmap_write(tcu->map, TCU_REG_TDFRc(timer->channel), next); in ingenic_tcu_cevt_set_next()
98 regmap_write(tcu->map, TCU_REG_TCNTc(timer->channel), 0); in ingenic_tcu_cevt_set_next()
[all …]
/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
[all …]
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3562.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/rockchip,rk3562-cru.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/rockchip,rk3562-power.h>
11 #include <dt-bindings/pinctrl/rockchip.h>
12 #include <dt-bindings/reset/rockchip,rk3562-cru.h>
13 #include <dt-bindings/soc/rockchip,boot-mode.h>
14 #include <dt-bindings/thermal/thermal.h>
[all …]

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