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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
27 wakeup-sourc
[all...]
/freebsd/sys/contrib/device-tree/Bindings/i2c/
H A Di2c-st.txt4 - compatible : Must be "st,comms-ssc-i2c" or "st,comms-ssc4-i2c"
5 - reg : Offset and length of the register set for the device
6 - interrupts : the interrupt specifier
7 - clock-names: Must contain "ssc".
8 - clocks: Must contain an entry for each name in clock-names. See the common
10 - A pinctrl state named "default" must be defined to set pins in mode of
14 - clock-frequency : Desired I2C bus clock frequency in Hz. If not specified,
17 - st,i2c-min-scl-pulse-width-us : The minimum valid SCL pulse width that is
19 - st,i2c-min-sda-pulse-width-us : The minimum valid SDA pulse width that is
21 - A pinctrl state named "idle" could be defined to set pins in idle state
[all …]
H A Dst,sti-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,sti-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
18 - st,comms-ssc-i2c
19 - st,comms-ssc4-i2c
30 clock-names:
33 clock-frequency:
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/freebsd/sys/contrib/dev/athk/
H A Ddfs_pattern_detector.h25 * TODO: this might need to be HW-dependent
30 * struct ath_dfs_pool_stats - DFS Statistics for global pools
43 * struct pulse_event - describing pulses reported by PHY
44 * @ts: pulse time stamp in us
46 * @width: pulse duration in us
48 * @chirp: chirp detected in pulse
53 u8 width; member
59 * struct radar_detector_specs - detector specs for a radar pattern type
61 * @width_min: minimum radar pulse width in [us]
62 * @width_max: maximum radar pulse width in [us]
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H A Ddfs_pri_detector.c27 #define DFS_POOL_STAT_DEC(c) (global_dfs_pool_stats.c--)
29 (MIN + PRI_TOLERANCE == MAX - PRI_TOLERANCE ? \
33 * struct pulse_elem - elements in pulse queue
41 * pde_get_multiple() - get number of multiples considering a given tolerance
42 * Return value: factor if abs(val - factor*fraction) <= tolerance, 0 otherwise
53 delta = (val < fraction) ? (fraction - val) : (val - fraction); in pde_get_multiple()
63 if ((fraction - remainder) <= tolerance) in pde_get_multiple()
73 * DOC: Singleton Pulse and Sequence Pools
97 singleton_pool_references--; in pool_deregister_ref()
105 list_del(&p->head); in pool_deregister_ref()
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/freebsd/sys/contrib/dev/mediatek/mt76/
H A Dmt76x02_dfs.c1 // SPDX-License-Identifier: ISC
154 struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd; in mt76x02_dfs_seq_pool_put()
156 list_add(&seq->head, &dfs_pd->seq_pool); in mt76x02_dfs_seq_pool_put()
158 dfs_pd->seq_stats.seq_pool_len++; in mt76x02_dfs_seq_pool_put()
159 dfs_pd->seq_stats.seq_len--; in mt76x02_dfs_seq_pool_put()
165 struct mt76x02_dfs_pattern_detector *dfs_pd = &dev->dfs_pd; in mt76x02_dfs_seq_pool_get()
168 if (list_empty(&dfs_pd->seq_pool)) { in mt76x02_dfs_seq_pool_get()
169 seq = devm_kzalloc(dev->mt76.dev, sizeof(*seq), GFP_ATOMIC); in mt76x02_dfs_seq_pool_get()
171 seq = list_first_entry(&dfs_pd->seq_pool, in mt76x02_dfs_seq_pool_get()
174 list_del(&seq->head); in mt76x02_dfs_seq_pool_get()
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Datmel,ebi.txt5 The EBI provides a glue-less interface to asynchronous memories through the SMC
10 - compatible: "atmel,at91sam9260-ebi"
11 "atmel,at91sam9261-ebi"
12 "atmel,at91sam9263-ebi0"
13 "atmel,at91sam9263-ebi1"
14 "atmel,at91sam9rl-ebi"
15 "atmel,at91sam9g45-ebi"
16 "atmel,at91sam9x5-ebi"
17 "atmel,sama5d3-ebi"
18 "microchip,sam9x60-ebi"
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H A Drenesas,rzg3e-xspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
14 the memory-mapping or the manual command mode.
19 - "jedec,spi-nor";
22 - $ref: /schemas/spi/spi-controller.yaml#
27 - const: renesas,r9a09g047-xspi # RZ/G3E
29 - items:
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/freebsd/share/man/man4/
H A Duart.41 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
53 .Bl -tag -compact -width 0x000000
72 EIA RS-232C (CCITT V.24) serial communications interface.
112 It contains the bus attachments and the low-level interrupt handler.
144 .Bl -bullet -compact
154 .Sh Pulse Per Second (PPS) Timing Interface
182 .Bl -tag -compact -offset "mmmm" -width "mmmm"
193 .Bl -tag -compact -offset "mmmm" -width "mmmm"
195 Invert the pulse (RS-232 logic low = ASSERT, high = CLEAR).
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/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstihxxx-b2120.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/clock/stih407-clks.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/media/c8sectpfe.h>
11 compatible = "gpio-leds";
12 led-red {
15 linux,default-trigger = "heartbeat";
17 led-green {
19 default-state = "off";
24 compatible = "simple-audio-card";
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H A Dstih418-b2199.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 compatible = "st,stih418-b2199", "st,stih418";
14 stdout-path = &sbc_serial0;
28 compatible = "gpio-leds";
29 led-red {
32 linux,default-trigger = "heartbeat";
34 led-green {
36 default-state = "off";
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H A Dstih410-b2260.dts1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "st,stih410-b2260", "st,stih410";
15 stdout-path = &uart1;
29 compatible = "gpio-leds";
30 led-user-green-1 {
33 linux,default-trigger = "heartbeat";
34 default-state = "off";
37 led-user-green-2 {
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/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/
H A Djedec,lpddr3-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr3-timings
19 Maximum DDR clock frequency for the speed-bin, in Hz.
20 Property is deprecated, use max-freq.
23 max-freq:
[all …]
H A Djedec,lpddr2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - elpida,ECB240ABACN
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H A Djedec,lpddr3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 - $ref: jedec,lpddr-props.yaml#
18 - items:
19 - enum:
20 - samsung,K3QF2F20DB
[all …]
H A Djedec,lpddr2-timings.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 const: jedec,lpddr2-timings
16 max-freq:
19 Maximum DDR clock frequency for the speed-bin, in Hz.
21 min-freq:
[all …]
/freebsd/sys/contrib/device-tree/src/arm/microchip/
H A Dsama5d3xcm.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * sama5d3xcm.dtsi - Device Tree Include file for SAMA5D3x CPU Module
14 stdout-path = "serial0:115200n8";
23 clock-frequency = <32768>;
27 clock-frequency = <12000000>;
34 cs-gpios = <&pioD 13 0>, <0>, <0>, <0>;
39 compatible = "atmel,tcb-timer";
44 compatible = "atmel,tcb-timer";
51 pinctrl-0 = <&pinctrl_ebi_addr &pinctrl_ebi_cs0>;
52 pinctr-name = "default";
[all …]
/freebsd/share/man/man4/man4.arm/
H A Dam335x_dmtpps.431 .Nd RFC 2783 Pulse Per Second API driver for AM335x systems
43 capture of Pulse Per Second (PPS) signals emitted by GPS receivers
50 on the leading edge of the PPS pulse.
89 .Bl -tag -width "GPMC_ADVn_ALE MMMM" -offset MMMM -compact
92 .It P8-7
94 .It P8-8
96 .It P8-9
98 .It P8-10
116 .Bd -literal
119 pinctrl-single,pins = <0x90 (PIN_INPUT | MUX_MODE2)>;
[all …]
/freebsd/sys/contrib/device-tree/Bindings/mtd/
H A Dlpc32xx-slc.txt4 - compatible: "nxp,lpc3220-slc"
5 - reg: Address and size of the controller
6 - nand-on-flash-bbt: Use bad block table on flash
7 - gpios: GPIO specification for NAND write protect
11 - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
12 - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
15 - nxp,wwidth: Write pulse width (W_WIDTH)
16 - nxp,whold: Write hold time (W_HOLD)
17 - nxp,wsetup: Write setup time (W_SETUP)
18 - nxp,rwidth: Read pulse width (R_WIDTH)
[all …]
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dssd1307fb.txt4 - compatible: Should be "solomon,<chip>fb-<bus>". The only supported bus for
7 - reg: Should contain address of the controller on the I2C bus. Most likely
9 - pwm: Should contain the pwm to use according to the OF device tree PWM
11 - solomon,height: Height in pixel of the screen driven by the controller
12 - solomon,width: Width in pixel of the screen driven by the controller
13 - solomon,page-offset: Offset of pages (band of 8 pixels) that the screen is
17 - reset-gpios: The GPIO used to reset the OLED display, if available. See
19 - vbat-supply: The supply for VBAT
20 - solomon,segment-no-remap: Display needs normal (non-inverted) data column
22 - solomon,col-offset: Offset of columns (COL/SEG) that the screen is mapped to.
[all …]
H A Dsolomon,ssd1307fb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Maxime Ripard <mripard@kernel.org>
11 - Javier Martinez Canillas <javierm@redhat.com>
17 - enum:
18 - solomon,ssd1305fb-i2c
19 - solomon,ssd1306fb-i2c
20 - solomon,ssd1307fb-i2c
21 - solomon,ssd1309fb-i2c
[all …]
/freebsd/sys/dev/ath/ath_hal/ar5212/
H A Dar5212phy.h1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
113 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */
145 #define AR_PHY_PLL_CTL_HALF 0x100 /* Half clock for 1/2 chan width */
146 #define AR_PHY_PLL_CTL_QUARTER 0x200 /* Quarter clock for 1/4 chan width */
158 #define AR_PHY_RX_DELAY 0x9914 /* analog pow-on time (100ns) */
162 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
212 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pinctrl/
H A Dpinctrl-mt6797.txt6 - compatible: Value should be one of the following.
7 "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
8 - reg: Should contain address and size for gpio, iocfgl, iocfgb,
10 - reg-names: An array of strings describing the "reg" entries. Must
12 - gpio-controller: Marks the device node as a gpio controller.
13 - #gpio-cells: Should be two. The first cell is the gpio pin number
17 - interrupt-controller: Marks the device node as an interrupt controller.
18 - #interrupt-cells: Should be two.
19 - interrupts : The interrupt outputs from the controller.
21 Please refer to pinctrl-bindings.txt in this directory for details of the
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dloongson,ls7a-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/loongson,ls7a-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Binbin Zhou <zhoubinbin@loongson.cn>
13 The Loongson PWM has one pulse width output signal and one pulse input
15 It can be found on Loongson-2K series cpus and Loongson LS7A bridge chips.
18 - $ref: pwm.yaml#
23 - const: loongson,ls7a-pwm
24 - items:
[all …]
/freebsd/contrib/ntp/html/
H A Dpps.html1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
6 <title>Pulse-Per-Second (PPS) Signal Interfacing</title>
10 <h3>Pulse-Per-Second (PPS) Signal Interfacing</h3>
14 <!-- #BeginDate format:En2m -->10-Mar-2014 05:17<!-- #EndDate -->
24 <li class="inline"><a href="#use">Using the Pulse-per-Second (PPS) Signal</a></li>
28 …-time epoch is indicated by a designated ASCII character such as carriage-return <tt>&lt;cr&gt;</t…
35 …inum minibox containing the the circuitry, serial connector and optional 12-V power connector. A …
36 …-width pulse at EIA levels and is for use with a timecode receiver or precision oscillator with a …
41 <h4 id="use">Using the Pulse-per-Second (PPS) Signal</h4>

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