Lines Matching +full:pulse +full:- +full:width
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
113 #define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calculation */
145 #define AR_PHY_PLL_CTL_HALF 0x100 /* Half clock for 1/2 chan width */
146 #define AR_PHY_PLL_CTL_QUARTER 0x200 /* Quarter clock for 1/4 chan width */
158 #define AR_PHY_RX_DELAY 0x9914 /* analog pow-on time (100ns) */
162 #define AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01F /* Mask for kcos_theta-1 for q correction */
212 #define AR_PHY_RADAR_0_INBAND 0x0000003e /* Inband pulse threshold */
214 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0 /* Pulse rssi threshold */
216 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000 /* Pulse height threshold */
230 #define AR_PHY_RADAR_2_MAXLEN 0x000000FF /* Max Pulse duration threshold */
232 #define AR_PHY_RADAR_2_RELSTEP 0x00001F00 /* Pulse relative step threshold */
234 #define AR_PHY_RADAR_2_RELPWR 0x003F0000 /* pulse relative power threshold */