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/linux/Documentation/devicetree/bindings/ptp/
H A Dfsl,ptp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale QorIQ 1588 timer based PTP clock
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,cpg-mstp-clocks.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,cpg-mstp-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Clock Pulse Generator (CPG) Module Stop (MSTP) Clocks
10 - Geert Uytterhoeven <geert+renesas@glider.be>
13 The Clock Pulse Generator (CPG) can gate SoC device clocks. The gates are
16 This device tree binding describes a single 32 gate clocks group per node.
18 and the clock index in the group, from 0 to 31.
23 - enum:
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/linux/Documentation/hwmon/
H A Dg760a.rst6 * Global Mixed-mode Technology Inc. G760A
12 http://www.gmt.com.tw/product/datasheet/EDS-760A.pdf
17 -----------
20 and performs closed-loop control of the fan speed.
23 consecutive speed pulses. The period is defined in terms of clock
24 cycle counts of an assumed 32kHz clock source.
30 from the measured speed pulse period by assuming again a 32kHz clock
31 source and a 2 pulse-per-revolution fan.
H A Dadm1026.rst16 - Philip Pokorny <ppokorny@penguincomputing.com> for Penguin Computing
17 - Justin Thiessen <jthiessen@penguincomputing.com>
20 -----------------
23 List of GPIO pins (0-16) to program as inputs
26 List of GPIO pins (0-16) to program as outputs
29 List of GPIO pins (0-16) to program as inverted
32 List of GPIO pins (0-16) to program as normal/non-inverted
35 List of GPIO pins (0-7) to program as fan tachs
39 -----------
45 16 general purpose digital I/O lines, eight (8) fan speed sensors (8-bit),
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H A Dadm9240.rst10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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H A Dpc87360.rst22 -----------------
27 - 0: None
28 - **1**: Forcibly enable internal voltage and temperature channels,
30 - 2: Forcibly enable all voltage and temperature channels, except in9
31 - 3: Forcibly enable all voltage and temperature channels, including in9
42 -----------
56 PC87360 - 2 2 - 0xE1
57 PC87363 - 2 2 - 0xE8
58 PC87364 - 3 3 - 0xE4
60 PC87366 11 3 3 3-4 0xE9
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/linux/Documentation/devicetree/bindings/net/
H A Dmdio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
16 MDIO bus must have a list of child nodes, one per device on the
17 bus. These should follow the generic ethernet-phy.yaml document, or
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
24 "#address-cells":
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/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
10 - Dong Aisheng <aisheng.dong@nxp.com>
16 are clocked by an asynchronous clock that can remain enabled in low
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
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/linux/Documentation/netlink/specs/
H A Ddpll.yaml1 # SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
2 ---
8 -
16 -
20 -
23 render-max: true
24 -
26 name: lock-status
31 -
37 -
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/linux/Documentation/devicetree/bindings/dpll/
H A Ddpll-device.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dpll/dpll-device.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Digital Phase-Locked Loop (DPLL) Device
10 - Ivan Vecera <ivecera@redhat.com>
13 Digital Phase-Locked Loop (DPLL) device is used for precise clock
16 output pins. Each DPLL channel can either produce pulse-per-clock signal
17 or drive ethernet equipment clock. The type of each channel can be
18 indicated by dpll-types property.
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/linux/drivers/media/i2c/
H A Dsaa711x_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * saa711x - Philips SAA711x video decoder register specifications
10 /* Video Decoder - Frontend part */
16 /* Video Decoder - Decoder part */
56 /* Audio clock generator part */
196 /* SAA7113 bit-masks */
230 /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
242 /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
297 /* 0x20 to 0x22 - Reserved */
304 /* 0x26 to 0x28 - Reserved */
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/linux/drivers/pwm/
H A Dpwm-tegra.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/pwm/pwm-tegra.c
5 * Tegra pulse-width-modulation controller driver
7 * Copyright (c) 2010-2020, NVIDIA Corporation.
8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
10 * Overview of Tegra Pulse Width Modulator Register:
11 * 1. 13-bit: Frequency division (SCALE)
12 * 2. 8-bit : Pulse division (DUTY)
13 * 3. 1-bit : Enable bit
15 * The PWM clock frequency is divided by 256 before subdividing it based
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H A Dpwm-imx1.c1 // SPDX-License-Identifier: GPL-2.0
3 * simple driver for PWM (Pulse Width Modulator) controller
43 ret = clk_prepare_enable(imx->clk_ipg); in pwm_imx1_clk_prepare_enable()
47 ret = clk_prepare_enable(imx->clk_per); in pwm_imx1_clk_prepare_enable()
49 clk_disable_unprepare(imx->clk_ipg); in pwm_imx1_clk_prepare_enable()
60 clk_disable_unprepare(imx->clk_per); in pwm_imx1_clk_disable_unprepare()
61 clk_disable_unprepare(imx->clk_ipg); in pwm_imx1_clk_disable_unprepare()
75 * Bootloader (u-boot or WinCE+haret) has programmed the PWM in pwm_imx1_config()
87 max = readl(imx->mmio_base + MX1_PWMP); in pwm_imx1_config()
90 writel(max - p, imx->mmio_base + MX1_PWMS); in pwm_imx1_config()
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/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -------
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
34 - Core clocks
35 - 0 0 APLL
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/linux/Documentation/devicetree/bindings/hwmon/
H A Dfan-common.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/hwmon/fan-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Naresh Solanki <naresh.solanki@9elements.com>
11 - Billy Tsai <billy_tsai@aspeedtech.com>
14 max-rpm:
20 min-rpm:
26 pulses-per-revolution:
28 The number of pulse from fan sensor per revolution.
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/linux/Documentation/ABI/testing/
H A Dsysfs-ptp14 hardware clock registered into the PTP class driver
21 This file contains the name of the PTP hardware clock
32 This file contains the PTP hardware clock's maximum
34 parts per billion.
41 Write integer to re-configure it.
48 alarms offer by the PTP hardware clock.
55 channels offered by the PTP hardware clock.
62 output channels offered by the PTP hardware clock.
69 offered by the PTP hardware clock.
77 physical clock is in use. Setting the value creates
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/linux/include/uapi/linux/
H A Dcomedi.h1 /* SPDX-License-Identifier: LGPL-2.0+ WITH Linux-syscall-note */
6 * COMEDI - Linux Control and Measurement Device Interface
7 * Copyright (C) 1998-2001 David A. Schleef <ds@schleef.org>
32 * NOTE: 'comedi_config --init-data' is deprecated
40 /* length of nth chunk of firmware data -*/
78 /* counters -- these are arbitrary values */
120 /* try to use a real-time interrupt while performing command */
123 /* wake up on end-of-scan events */
166 #define TRIG_INT 0x00000080 /* trigger on comedi-internal signal N */
179 #define SDF_PWM_HBRIDGE 0x0100 /* PWM is signed (H-bridge) */
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H A Ddpll.h1 /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
2 /* Do not edit directly, auto-generated from: */
4 /* YNL-GEN uapi header */
13 * enum dpll_mode - working modes a dpll can support, differentiates if and how
25 DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
29 * enum dpll_lock_status - provides information of dpll device lock status,
36 * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
38 * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
39 * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
50 DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
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/linux/drivers/net/phy/
H A Dbcm-phy-ptp.c1 // SPDX-License-Identifier: GPL-2.0
16 #include "bcm-phy-lib.h"
158 #define BCM_SKB_CB(skb) ((struct bcm_ptp_skb_cb *)(skb)->cb)
161 #define BCM_MAX_PULSE_8NS ((1U << 9) - 1)
162 #define BCM_MAX_PERIOD_8NS ((1U << 30) - 1)
165 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
192 ts->tv_sec = (hb[3] << 16) | hb[2]; in bcm_ptp_get_framesync_ts()
193 ts->tv_nsec = (hb[1] << 16) | hb[0]; in bcm_ptp_get_framesync_ts()
213 /* trigger framesync - must have 0->1 transition. */ in bcm_ptp_framesync()
245 return reg & INTC_FSYNC ? 0 : -ETIMEDOUT; in bcm_ptp_framesync_ts()
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/linux/arch/mips/include/asm/sn/
H A Dioc3.h1 /* SPDX-License-Identifier: GPL-2.0 */
50 u8 fill0[0x151 - 0x142 - 1];
56 u8 fill1[0x159 - 0x153 - 1];
62 u8 fill2[0x16a - 0x15b - 1];
67 u8 fill3[0x170 - 0x16b - 1];
153 u32 pad1[(0x20000 - 0x00154) / 4];
157 u32 pad2[(0x40000 - 0x20180) / 4];
160 u32 ssram[(0x80000 - 0x40000) / 4];
163 0x80000 - Access to the generic devices selected with DEV0
165 0xA0000 - Access to the generic devices selected with DEV1
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/linux/drivers/i2c/busses/
H A Di2c-st.c1 // SPDX-License-Identifier: GPL-2.0-only
117 /* SSC Clock Prescaler */
131 * struct st_i2c_timings - per-Mode tuning parameters
139 * @sda_pulse_min_limit: I2C SDA pulse mini width limit
153 * struct st_i2c_client - client specific data
154 * @addr: 8-bit target addr, including r/w bit
171 * struct st_i2c_dev - private data of the controller
177 * @clk: hw ssc block clock
179 * @scl_min_width_us: SCL line minimum pulse width in us
180 * @sda_min_width_us: SDA line minimum pulse width in us
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/linux/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
91 * Controller (UDC) Control/Status register end-point 0
94 * Controller (UDC) Control/Status register end-point 1
97 * Controller (UDC) Control/Status register end-point 2
100 * Controller (UDC) Data register end-point 0
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/linux/drivers/video/fbdev/
H A Dpxa3xx-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
73 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
74 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
90 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
94 #define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
96 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
97 #define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
99 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
100 #define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
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/linux/drivers/hwmon/
H A Dnpcm750-pwm-fan.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2014-2018 Nuvoton Technology corporation.
7 #include <linux/hwmon-sysfs.h>
147 * Get Fan Tach Timeout (base on clock 214843.75Hz, 1 cnt = 4.654us)
149 * (The minimum FAN speed could to support ~640RPM/pulse 1,
150 * 320RPM/pulse 2, ...-- 10.6Hz)
154 #define NPCM7XX_FAN_TCPA (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
155 #define NPCM7XX_FAN_TCPB (NPCM7XX_FAN_TCNT - NPCM7XX_FAN_TIMEOUT)
224 mutex_lock(&data->pwm_lock[module]); in npcm7xx_pwm_config_set()
227 iowrite32(val, NPCM7XX_PWM_REG_CMRx(data->pwm_base, module, pwm_ch)); in npcm7xx_pwm_config_set()
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H A Dg762.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * g762 - Driver for the Global Mixed-mode Technology Inc. fan speed
15 * http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf
27 * http://www.gmt.com.tw/product/datasheet/EDS-762_3.pdf
36 #include <linux/hwmon-sysfs.h>
67 #define G762_REG_FAN_CMD1_FAN_MODE 0x10 /* fan mode: closed/open-loop */
68 #define G762_REG_FAN_CMD1_CLK_DIV_ID1 0x08 /* clock divisor value */
71 #define G762_REG_FAN_CMD1_PULSE_PER_REV 0x01 /* pulse per fan revolution */
73 #define G761_REG_FAN_CMD2_FAN_CLOCK 0x20 /* choose internal clock*/
92 /* Register data is read (and cached) at most once per second. */
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